Logical DRC constraints

14.1. Logical DRC constraints

DRC constraints exist in library. DRC constraints can’t be relaxed. They can be chosen from library. These constraints are imposed upon the design by requirements specified in the target technology library. This presides over optimization constraints to realize a functional design.

.lib: Library level attributes

7.2.2. .lib: Library level attributes

Library level attributes section explains technolgy type, date, revision. It also gives units of volt, amps, time, capacitance etc which are used in the library.

 

Eg.:

  /* General Attributes */

  technology                        (cmos);

  delay_model                     : table_lookup;

  in_place_swap_mode              : match_footprint;

  library_features                  (report_delay_calculation,report_power_calculation);

 

  /* Units Attributes */

  time_unit                       : "1ns";

  leakage_power_unit              : "1nW";

  voltage_unit                    : "1V";

  current_unit                    : "1mA";

  pulling_resistance_unit         : "1kohm";

  capacitive_load_unit              (1,ff);

Logic Library

7.1 Logic Library

Logic synthesis relevant information are contained in logic libraries. Logic libraries does not contain any physical information of the logic gates. Logic library is a text file. Initially its development were done by a company called “liberty” which was later got acquired by EDA company Synopsys. Hence usual extension of logic libray is .lib and is known as liberty format logic library. This is now universally accepted and used by all fabrication houses and EDA companies.

 

Logic library has timing, area and power information pertaining to all logic gates. These characteristics include information such as cell names, pin names, delay arcs, and pin loading.

 

The technology library also defines the conditions such as the maximum transition time for nets, maximum capacitance and maximim fanout loading. These conditions are called design rule constraints.

 

In addition to cell information and design rule constraints, specify the operating conditions and wire load models specific to that technology are specified in technology library.

 

Net delay models in logic libraries are calculated from different models known as:

Ø  Nonlinear delay models (NLDMs)

Ø  Composite Current Source (CCS) models

 

7.2 Basics of Logic Library (.lib)

The contents of logic library can be broadly classified as below:

Ø  Library group

Ø  Library level attributes

Ø  Environment Description

Ø  Cell description

 

7.2.1. Library group

This gives part specifies general information such as library name regarding library.

Avoid latch inference, Use Constants, General Coding guidelines for ASIC synthesis

5.2.15. Avoid latch inference

Ø  “if-else” statements must be end with ‘else’ statements. Else ‘unintentional latches’ will be realized (at output) due to the missing ‘else’ statement at the end.

Ø  Same is true for ‘case’ statement. ‘default’ statement must be added.

 

Work Around:

Either include all possible combination of inputs or initialise the value before the loop starts.

Eg.:

if(z)   a=b;

Above code will infer a latch. Because if z=1, value of ‘a’ is defined. But if z=0 value of ‘a’ is not specified. Hence it is assumed that  previous value has to be retained and hence latch is infered.

 

Eg.:

module latch_inf_test(a, x, y, t, out);

input [2:0] a;

input x, y, t;

output out; reg out;

 

always @(a or x or y or t)

begin

case(a)

                   3’b001:out=x;

                   3’b010:out=y;

                   3’b100:out=t;

endcase

end

endmodule

 

 

Eg.:

module case_latch(dout,sel,a,b,c);

input [1:0] sel;

input a,b,c;

output dout;

reg dout;

 

always @(a or b or c or sel)

begin

case (sel)

2'b00 : dout = a;

2'b01 : dout = b;

2'b10 : dout = c;

endcase

end

endmodule

Preventing a Latch by Assigning a Default Value

module case_default(dout,sel,a,b,c);

input [1:0] sel;

input a,b,c;

output dout;

reg dout;

 

always @(a or b or c or sel)

begin

case (sel)

2'b00 : dout = a;

2'b01 : dout = b;

2'b10 : dout = c;

default : dout = 1'b0;

endcase

end

endmodule

5.2.16. Use Constants

Use constants instead of hard coded numeric values.

Below coding style is not recommended:

wire [15:0] input_bus;

reg [15:0] output bus;

 

Recommended coding style:

‘define INPUT_BUS_WIDTH 16

‘define OUTPUT_BUS_WIDTH 16

wire [INPUT_BUS_WIDTH-1:0] input_bus;

reg [OUTPUT_BUS_WIDTH-1:0] output_bus;

 

Keep constants and parameters definitions in separate file with naming convention such as design_name.constants.v and design_name.parameters.v

 

 

5.2.17. General Coding guidelines for ASIC synthesis

Ø  “Inference” of the logic should be given higher priority compared to instantiation of the logic.

Ø  File name and module name should be same.

Ø  A file should have only one module.

Ø  Use lowercase letters for ports, variables and signal names.

Ø  Use uppercase for constants, user defined types.

References

[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005

[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009

[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009

Reset logic guidelines, Registered outputs and Incomplete sensitivity list

5.2.12. Reset logic guidelines

Synchronous Reset:

Advantages:

Ø  Easy to synthesize, just another synchronous input to the design.

Disadvantages:

Ø  Require a free running clock. At power-up clock is must for reset.

Asynchronous Reset:

Advantages:

Ø  Doesn’t require a free running clock.

Ø  Uses separate input on flip flop, so it doesn’t affect flop data timing.

Disadvantages:

Ø  Harder to implement. Considered as high fanout net

Ø  STA, simulation, DFT becomes difficult

 

5.2.13. Registered outputs

All outputs should be registered and combinational logic should be either at the input section or in between two registered stages of a module.

 

5.2.14. Incomplete sensitivity list

Sensitive list should contain all inputs. If inputs are missed in the sensitivity list, then the changes of that inputs will not be recognized by simulator. Synthesized logic in most cases may correct for the blocks containing incomplete sensitivity list. But this may cause simulation mismatches between source RTL and synthesized netlist. Generally synthesis tools issue a warning for the “always” block having incomplete sensitivity list. Registers can also be added in the sensitive list.

References

[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005

[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009

[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009

Clock logic guidelines

5.2.11. Clock logic guidelines

In case of multiple clocks in the design, make sure that clock generation and reset logics are written in one module for better handling in synthesis. If a clock is used in different modules of different heirarchy then keep clock names common across all the modules. This makes constraining that clock easier and also supports better handling of synthesis scripts.

 

Ø  Don’t use mixed clock edges

mixing of edge sensitive and level sensitive lists are not allowed. Below code is a wrong one.

always @(posedge clk or posedge rst)

 

Ø  Avoid clock buffers or any other logic

If any signal crosses multiple clock domains having different clock frequencies then those signals must be properly synchronised with synchronous logic. Synthesis tools can’t optimize any timing paths between asynchronous clock domains.

References

[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005

[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009

[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009

Technology independent RTL coding

5.2.9. Technology independent RTL coding

Write HDL code in technology independent fasion. This helps reusage of the HDL code for any technology node. Do not hard code logic gates from the technology library unless it is necessary to meet critical timing issues.

 

5.2.10. Pads separate from core logic

Pads are instantiated like any other module instantiation. If design has large number of I/O pads it is recommended to keep the pad instantiations in a separate file. Note that pads are technology dependant and hence the above recommendation!

References

[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005

[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009

[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009

FSM synthesis guidelines

5.2.7 FSM synthesis guidelines

If you are using state machine for coding then take care to separate it from other logic. This helps synthesis tools to synthesize and optimize FSM logic much better. Use “parameter” in Verilog to describe state names. An “always” block should have all the combinational logic for computing the next state.

 

References
[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005

[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009

[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009

Proper partitioning for synthesis

5.2.6. Proper partitioning for synthesis

 

Properly partition the top level design based on functionality. Keep related combinational logic in same module. It is not recommended to add glue logic at top level of the module. Hierarchical designs are good but unnecessary hierarchies may limit the optimizations across the hierarchies. It is practically observed that deeper hierarchies cause miserably failing boundary optimizations due to increased number of either setup or hold fixing buffer insertion. In such cases ungrouping or flattening hierarchy command can be used to flatten the unwanted hierarchies before compiling the design to achieve better results.

 

References
[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005

[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009

[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009

How Hardware s Inferred- if vs case

5.2.5. if vs case

Multiflexer is faster circuit. Therefore is priority encoding structure is not required then use ‘case’ staements instead of ‘if-else’ statement.

Use late arriving signal early in an ‘if-else’ loop to keep these late arriving signals with critical timing closest to the output of a logic block.

 

 

References
[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005

[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009

[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009

How hardware is inferred - Combo Logics

5.2.4. Combo Logics

If unknown ‘x’ or ‘z’ is assigned then it will be realized into tristate buffer. So avoid using ‘x’ and ‘z’. usage of these may mislead synthesis.

Eg.:

assign tri_out=en ? tri_in : 1b’z;

 

 

How hardware is inferred?

5.2. How hardware is inferred?

5.2.1 Register inference

Whenever there is a ‘posedge’ or ‘negedge’ construct synthesis tool infers a flip flop.

 

always @(posedge clk)

output_reg <= data;

 

Above code infers D-flip flop.

 

Asynchronous reset :

 

module async_rst(clk,rst,data,out);

input clk, rst, data;

output out;

reg out;

 

always @(posedge clk or negedge rst)

begin

if(!rst)

out<=1’b0;

else    

out<=data;

end

endmodule

 

In above case the sensitivity list includes both clock and the rst and hence it infers a asynchronous reset flip flop. rst has negedge in sensitivity list and hence same should be checked in the code.

 

Synchronous Reset:

 

module sync_rst(clk,rst,data,out);

input clk, rst, data;

output out;

reg out;

 

always @(posedge clk)

begin

if(!rst)

out<=1’b0;

else

out<=data;

end

endmodule

 

In above case the sensitivity list doesn’t include ‘rst’ and hence it infers a synchronous reset flip flop.

 

5.2.2 Mux Inference

“if else” loop infers a mux. 

eg.:

 if(sel) z=a; else z=b;

 

General case statement infers a mux. If case statement is a overlapping structure then priority encoder in infered.  Case statements only works with true values of 0 or 1.

 

 

5.2.3. Priority Encoder Inference

Multiple if statements with multiple branches result in the creation of priority encoder structure.

“if else if” infers priority encoder.