Clock logic guidelines

5.2.11. Clock logic guidelines

In case of multiple clocks in the design, make sure that clock generation and reset logics are written in one module for better handling in synthesis. If a clock is used in different modules of different heirarchy then keep clock names common across all the modules. This makes constraining that clock easier and also supports better handling of synthesis scripts.

 

Ø  Don’t use mixed clock edges

mixing of edge sensitive and level sensitive lists are not allowed. Below code is a wrong one.

always @(posedge clk or posedge rst)

 

Ø  Avoid clock buffers or any other logic

If any signal crosses multiple clock domains having different clock frequencies then those signals must be properly synchronised with synchronous logic. Synthesis tools can’t optimize any timing paths between asynchronous clock domains.

References

[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005

[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009

[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009

Technology independent RTL coding

5.2.9. Technology independent RTL coding

Write HDL code in technology independent fasion. This helps reusage of the HDL code for any technology node. Do not hard code logic gates from the technology library unless it is necessary to meet critical timing issues.

 

5.2.10. Pads separate from core logic

Pads are instantiated like any other module instantiation. If design has large number of I/O pads it is recommended to keep the pad instantiations in a separate file. Note that pads are technology dependant and hence the above recommendation!

References

[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005

[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009

[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009

Blocking vs non-blocking-race condition

5.2.8. Blocking vs non-blocking-race condition

      Never mix a description of combinational (blocking) construct with sequential (nonblocking).

      Blocking: combinational àracing

Since the final outputs depend on the order in which the assignments are evaluated, blocking assignments within sequential block may cause race condition.

      Nonblocking: sequential àNo race condition

Nonblockng assignments closely resemble hardware as they are order independent.

      Most of the applications which require data transfer within module required to be written using non-blocking assignment statement.

 

References

[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005

[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009

[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009

FSM synthesis guidelines

5.2.7 FSM synthesis guidelines

If you are using state machine for coding then take care to separate it from other logic. This helps synthesis tools to synthesize and optimize FSM logic much better. Use “parameter” in Verilog to describe state names. An “always” block should have all the combinational logic for computing the next state.

 

References
[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005

[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009

[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009

Proper partitioning for synthesis

5.2.6. Proper partitioning for synthesis

 

Properly partition the top level design based on functionality. Keep related combinational logic in same module. It is not recommended to add glue logic at top level of the module. Hierarchical designs are good but unnecessary hierarchies may limit the optimizations across the hierarchies. It is practically observed that deeper hierarchies cause miserably failing boundary optimizations due to increased number of either setup or hold fixing buffer insertion. In such cases ungrouping or flattening hierarchy command can be used to flatten the unwanted hierarchies before compiling the design to achieve better results.

 

References
[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005

[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009

[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009

How Hardware s Inferred- if vs case

5.2.5. if vs case

Multiflexer is faster circuit. Therefore is priority encoding structure is not required then use ‘case’ staements instead of ‘if-else’ statement.

Use late arriving signal early in an ‘if-else’ loop to keep these late arriving signals with critical timing closest to the output of a logic block.

 

 

References
[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005

[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009

[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009

How hardware is inferred - Combo Logics

5.2.4. Combo Logics

If unknown ‘x’ or ‘z’ is assigned then it will be realized into tristate buffer. So avoid using ‘x’ and ‘z’. usage of these may mislead synthesis.

Eg.:

assign tri_out=en ? tri_in : 1b’z;

 

 

How hardware is inferred?

5.2. How hardware is inferred?

5.2.1 Register inference

Whenever there is a ‘posedge’ or ‘negedge’ construct synthesis tool infers a flip flop.

 

always @(posedge clk)

output_reg <= data;

 

Above code infers D-flip flop.

 

Asynchronous reset :

 

module async_rst(clk,rst,data,out);

input clk, rst, data;

output out;

reg out;

 

always @(posedge clk or negedge rst)

begin

if(!rst)

out<=1’b0;

else    

out<=data;

end

endmodule

 

In above case the sensitivity list includes both clock and the rst and hence it infers a asynchronous reset flip flop. rst has negedge in sensitivity list and hence same should be checked in the code.

 

Synchronous Reset:

 

module sync_rst(clk,rst,data,out);

input clk, rst, data;

output out;

reg out;

 

always @(posedge clk)

begin

if(!rst)

out<=1’b0;

else

out<=data;

end

endmodule

 

In above case the sensitivity list doesn’t include ‘rst’ and hence it infers a synchronous reset flip flop.

 

5.2.2 Mux Inference

“if else” loop infers a mux. 

eg.:

 if(sel) z=a; else z=b;

 

General case statement infers a mux. If case statement is a overlapping structure then priority encoder in infered.  Case statements only works with true values of 0 or 1.

 

 

5.2.3. Priority Encoder Inference

Multiple if statements with multiple branches result in the creation of priority encoder structure.

“if else if” infers priority encoder.

Synthesizable and Non-Synthesizable Verilog constructs

5.1. Synthesizable and Non-Synthesizable Verilog constructs

	Synthesizable	Non-Synthesizable
Basic	Identifiers, escaped identifiers, Sized constants (b, o, d, h), Unsized constants (2'b11, 3'07, 32'd123, 8'hff), Signed constants (s) 3'bs101, module, endmodule, macromodule, ANSI-style module, task, and function port lists	system tasks, real constants
Data types	wire, wand, wor, tri, triand, trior, supply0, supply1, trireg (treated as wire), reg, integer, parameter, input, output, inout, memory(reg [7:0] x [3:0];), N-dimensional arrays,	real, time, event, tri0, tri1
Module instances	Connect port by name, order, Override parameter by order, Override parameter by name, Constants connected to ports, Unconnected ports, Expressions connected to ports,	Delay on built-in gates
Generate statements	if,case,for generate, concurrent begin end blocks, genvar,
Primitives	and, or, nand, nor, xor, xnor,not, notif0, notif1, buf, bufif0, bufif1, tran,	User defined primitives (UDPs), table, pullup, pulldown, pmos, nmos, cmos, rpmos, rnmos, rcmos, tranif0, tranif1, rtran, rtranif0, rtranif1,
Operators and expressions	+, - (binary and unary)
Bitwise operations	&, |, ^, ~^, ^~
Reduction operations	&, |, ^, ~&, ~|, ~^, ^~, !, &&, || , ==, !=, <, <=, >, >=, <<, >>, <<< >>>, {}, {n{}}, ?:, function call	===, !==
Event control	event or, @ (partial), event or using comma syntax, posedge, negedge (partial),	Event trigger (->), delay and wait (#)
Bit and part selects	Bit select, Bit select of array element, Constant part select, Variable part select ( +:, -:), Variable bit-select on left side of an assignment
Continuous assignments	net and wire declaration, assign	Using delay
Procedural blocks	always (exactly one @ required),	initial
Procedural statements	;, begin-end, if-else, repeat, case, casex, casez, default, for-while-forever-disable(partial),	fork, join
Procedural assignments	blocking (=), non-blocking (<=)	force, release
Functions and tasks	Functions, tasks
Compiler directives	`define, `undef, `resetall, `ifndef, `elsif, `line, `ifdef, `else, `endif, `include

References
[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005

[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009

[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009

RTL Coding for Logic Synthesis

5. RTL Coding for Logic Synthesis

References

[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005

[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009

[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009