ASIC-System on Chip-VLSI Design: Digital design

Showing posts with label Digital design. Show all posts

Draw XNOR gate using MUX.

Draw XOR gate using MUX.

Draw NOR gate using MUX.

Draw NAND gate using MUX.

Draw OR gate using 2:1 MUX.

Applying similar concept of AND gate using 2:1 MUX, make either of input A or B as select line of MUX, connect other input to 0th input line. 1st input of the MUX is always tied to logic 1.

Related faq

AND gate using MUX
NAND gate using MUX
NOR gate using MUX
XOR gate using MUX
XNOR using MUX

How to get AND gate using 2:1 MUX?

Look at the truth table of AND gate. When any of the one input is zero output is always zero (or same as that input); when the other input is one, output is dependent on the other input and is same as the other input. Using this property we can draw AND gate in four different ways using 2:1 MUX as shown in the above figure.

Similar concept can be applied to create all basic gates from 2:1 MUX. I will publish all these in coming blog posts along with the elaborated figures.

Related faq

OR gate using MUX
NAND gate using MUX
NOR gate using MUX
XOR gate using MUX
XNOR using MUX

Metastability, Reset

What is metastability?

When setup or hold window is violated in an flip flop then signal attains a unpredictable value or state known as metastability.

What is MTBF? What it signifies?

MTBF-Mean Time Before Failure

Average time to next failure

How chance of metastable state failure can be reduced?

Lowering clock frequency
Lowering data speed
Using faster flip flop

What are the advantages of using synchronous reset ?

No metastability problem with synchronous reset (provided recovery and removal time for reset is taken care).

Simulation of synchronous reset is easy.

What are the disadvantages of using synchronous reset ?

Synchronous reset is slow.

Implementation of synchronous reset requires more number of gates compared to asynchronous reset design.

An active clock is essential for a synchronous reset design. Hence you can expect more power consumption.

What are the advantages of using asynchronous reset ?

Implementation of asynchronous reset requires less number of gates compared to synchronous reset design.

Asynchronous reset is fast.

Clocking scheme is not necessary for an asynchronous design. Hence design consumes less power. Asynchronous design style is also one of the latest design options to achieve low power. Design community is scrathing their head over asynchronous design possibilities.

What are the disadvantages of using asynchronous reset ?

Metastability problems are main concerns of asynchronous reset scheme (design).

Static timing analysis and DFT becomes difficult due to asynchronous reset.

What are the 3 fundamental operating conditions that determine the delay characteristics of gate?
How operating conditions affect gate delay?

Process
Voltage
Temperature

Click here to read more.

Is verilog/VHDL is a concurrent or sequential language?

Verilog and VHDL both are concurrent languages.

Any hardware descriptive language is concurrent in nature.

In a system with insufficient hold time, will slowing down the clock frequency help?

Making data path slower can help hold time but it may result in setup violation.

In a system with insufficient setup time, will slowing down the clock frequency help?

Yes.

Making data path faster can also help setup time but it may result in hold violation.

What is the difference between a latch and a flip-flop?

Both latches and flip-flops are circuit elements whose output depends not only on the present inputs, but also on previous inputs and outputs.

They both are hence referred as "sequential" elements.

In electronics, a latch, is a kind of bistable multi vibrator, an electronic circuit which has two stable states and thereby can store one bit of of information. Today the word is mainly used for simple transparent storage elements, while slightly more advanced non-transparent (or clocked) devices are described as flip-flops. Informally, as this distinction is quite new, the two words are sometimes used interchangeably. [wiki]

In digital circuits, a flip-flop is a kind of bistable multi vibrator, an electronic circuit which has two stable states and thereby is capable of serving as one bit of memory. Today, the term flip-flop has come to generally denote non-transparent (clocked or edge-triggered) devices, while the simpler transparent ones are often referred to as latches.[wiki]

A flip-flop is controlled by (usually) one or two control signals and/or a gate or clock signal.

Latches are level sensitive i.e. the output captures the input when the clock signal is high, so as long as the clock is logic 1, the output can change if the input also changes.

Flip-Flops are edge sensitive i.e. flip flop will store the input only when there is a rising or falling edge of the clock.

A positive level latch is transparent to the positive level(enable), and it latches the final input before it is changing its level(i.e. before enable goes to '0' or before the clock goes to -ve level.)

A positive edge flop will have its output effective when the clock input changes from '0' to '1' state ('1' to '0' for negative edge flop) only.

Latches are faster, flip flops are slower.

Latch is sensitive to glitches on enable pin, whereas flip-flop is immune to glitches.

Latches take less gates (less power) to implement than flip-flops.

D-FF is built from two latches. They are in master slave configuration.

Latch may be clocked or clock less. But flip flop is always clocked.

For a transparent latch generally D to Q propagation delay is considered while for a flop clock to Q and setup and hold time are very important.

Synthesis perspective: Pros and Cons of Latches and Flip Flops

In synthesis of HDL codes inappropriate coding can infer latches instead of flip flops. Eg.:"if" and "case" statements. This should be avoided sa latches are more prone to glitches.

Latch takes less area, Flip-flop takes more area ( as flip flop is made up of latches) .

Latch facilitate time borrowing or cycle stealing whereas flip flops allow synchronous logic.

Latches are not friendly with DFT tools. Minimize inferring of latches if your design has to be made testable. Since enable signal to latch is not a regular clock that is fed to the rest of the logic. To ensure testability, you need to use OR gate using "enable" and "scan_enable" signals as input and feed the output to the enable port of the latch. [ref]

Most EDA software tools have difficulty with latches. Static timing analyzers typically make assumptions about latch transparency. If one assumes the latch is transparent (i.e.triggered by the active time of clock,not triggered by just clock edge), then the tool may find a false timing path through the input data pin. If one assumes the latch is not transparent, then the tool may miss a critical path.

If target technology supports a latch cell then race condition problems are minimized. If target technology does not support a latch then synthesis tool will infer it by basic gates which is prone to race condition. Then you need to add redundant logic to overcome this problem. But while optimization redundant logic can be removed by the synthesis tool ! This will create endless problems for the design team.

Due to the transparency issue, latches are difficult to test. For scan testing, they are often replaced by a latch-flip-flop compatible with the scan-test shift-register. Under these conditions, a flip-flop would actually be less expensive than a latch. Read a good article on problems of latch published in eetimes long back !!

Flip flops are friendly with DFT tools. Scan insertion for synchronous logic is hassle free.

Digital design Interview Questions

If inverted output of D flip-flop is connected to its input how the flip-flop behaves?
Design a circuit to divide input frequency by 2?
Design a divide by two counter using D-Latch.
Design a divide-by-3 sequential circuit with 50% duty cycle.
What are the different types of adder implementation?
Draw a Transmission Gate-based D-Latch?
Give the truth table for a Half Adder. Give a gate level implementation of the same.
Design an OR gate from 2:1 MUX.
What is the difference between a LATCH and a FLIP-FLOP?
Design a D Flip-Flop from two latches.
Design a 2 bit counter using D Flip-Flop.
What are the two types of delays in any digital system
Design a Transparent Latch using a 2:1 Mux.
Design a 4:1 Mux using 2:1 Mux's.
What is metastable state? How does it occur?
What is metastablity?
Design a 3:8 decoder
Design a FSM to detect sequence "101" in input sequence
Convert NAND gate into Inverter in two different ways.
Design a D and T flip flop using 2:1 mux only.
Design D Latch from SR flip-flop.
Define Clock Skew, Negative Clock Skew, Positive Clock Skew?
What is race condition? How it occurs? How to avoid it?
Design a 4 bit Gray Counter?
Design 4-bit synchronous counter, asynchronous counter?
Design a 16 byte asynchronous FIFO?
What is the difference between a EEPROM and FLASH?
What is the difference between a NAND-based Flash and NOR-based Flash?
Which one is good: asynchronous reset or synchronous reset? Why?
Design a simple circuit based on combinational logic to double the output frequency.
What is the difference between flip-flop and latch?
Implement comparator using combinational logic, that compares two 2-bit numbers A and B. The comparator should have 3 outputs: A > B, A < a =" B.">
Give two ways of converting a two input NAND gate to an inverter?
What is the difference between mealy and moore state-machines?
What is the difference between latch based design and flip-flop based design?
What is metastability and how to prevent it?
Design a four-input NAND gate using only two-input NAND gates.
Why are most interrupts active low?
How do you detect if two 8-bit signals are same?
7 bit ring counter's initial state is 0100010. After how many clock cycles will it return to the initial state?
Design all the basic gates NOT, AND, OR, NAND, NOR, XOR, XNOR using 2:1 Multiplexer.
How will you implement a full subtractor from a full adder?
In a 3-bit Johnson's counter what are the unused states?
What is difference between RAM and FIFO?
What is an LFSR? List a few of its industry applications.
Implement the following circuits:
(a) 3 input NAND gate using minimum number of 2 input NAND gates
(b) 3 input NOR gate using minimum number of 2 input NOR gates
(c) 3 input XNOR gate using minimum number of 2 input XNOR gates assuming 3 inputs A,B,C?
Design a D-latch using (a) using 2:1 Mux (b) from S-R Latch?
How to implement a Master Slave flip flop using a 2 to 1 mux?
How many 2 input xor's are needed to inplement 16 input parity generator?
Convert xor gate to buffer and inverter.
Difference between onehot and binary encoding?
What are different ways to synchronize between two clock domains?
How to calculate maximum operating frequency?
How to find out longest path?
How to achieve 180 degree exact phase shift?
What is significance of ras and cas in SDRAM?
Tell some of applications of buffer?
Implement an AND gate using mux?
What will happen if contents of register are shifter left, right?
What is the basic difference between analog and digital design?
What advantages do synchronous counters have over asynchronous counters?
What types of flip-flops can be used to implement the memory elements of a counter?
What are the advantages of using a microprocessor to implement a counter rather than the conventional method (flip-flop and logic gates)?
What is the principal advantage of Gray Code over straight (conventional) binary?
What does Pipelining do?
Design divide by 2, divide by 3 circuit with equal duty cycle.
How many 4:1 mux do you need to design a 8:1 mux?
What is D-Word, Q-word?
Define Moore, Mealy state machines. Which one is good for timing?
Design a FSM to detect 10110. What is the minimum number of flops required?
Design a simple circuit based on combinational logic to double the output frequency.
Design a 2bit up/down counter with clear using gates. (No verilog or vhdl)
Design a finite state machine to give a modulo 3 counter when x=0 and modulo 4 counter when x=1.
Minimize: S= A' + AB
What is the function of a D-flipflop, whose inverted outputs are connected to its input?
How to synchronize control signals and data between two different clock domains?
Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
In what cases do you need to double clock a signal before presenting it to a synchronous state machine?
How many bit combinations are there in a byte?
What are the different Adder circuits you studied?
Give the truth table for a Half Adder. Give a gate level implementation of the same.
Convert 65(Hex) to Binary
Convert a number to its two's compliment and back.
What is the 1's and 2's complement of the decimal number 25.
If A?B=C and C?A=B then what is the boolean operator ?

ASIC-System on Chip-VLSI Design