Latest VLSI Back-end Physical Design Interview Questions - Semiconductor Product Company Team 2 and 3

Interview Questions from Major Semiconductor Product Company Team 2:
(These questions were asked by tech lead with ~6-10 years of experience)
  • What are PLL related specification for placement?
  • What is static IR drop?
  • What are different types of dynamic IR?
  • Is it average, peak to peak? Or RMS? What are all these?

New Clock Gating Method That Does Not Introduce Clock Skew



FULLY SYNCHRONOUS DESIGN

Fully Synchronous Design (Abbreviated FSD) refers to a digital system having a single clock signal for all Flip Flops (Abbreviated FF) within the system.

In such a design, all FFs are clocked all together by this single clock signal : should a design comprise 1200 FFs, they are clocked together by the same clock signal.

If one is planning an ASIC, then the ASIC manufacturer is responsible for designing a clock tree for his particular die, offering a known (and minimal) clock skew.

The ASIC manufacturer is also responsible for the design of a reset tree for his particular die.

To All VLSI Training Institutes

    I have been seeing promotional comments written by multiple reputed VLSI training centers in comment section of pages or articles. Despite my humble request this is still continuing. Let me clearly tell all those people that none of these comments will be published unless yo follow standard guideline i have put forward in 'training' page. My intention is not to dis-respect you , rather to improve the genuineness of  your business. 

Latest VLSI Back-end Physical Design Interview Questions - Semiconductor Product Company Team 1

I have given below physical design interview questions asked in one of the major semiconductor companies located in Bangalore. This semiconductor giant has multiple independent teams and they evaluate candidates as per their project requirements. Irrespective of the company, these questions are very important if you intend to grow in VLSI(Very Large Scale Integration) physical design domain. 

I welcome answers from my readers for these questions. Best discussions will be published below each questions. In this way please help improve knowledge of the seekers and let this bit help from us may get blessed from those in need. 

These are difficult times due to the impact of COVID-19 pandemic. Updating our knowledge is key for survival and success !!

New Advanced Semiconductor Fab from TSMC in USA


source: TSMC

TSMC Announces Intention to Build and Operate an Advanced Semiconductor Fab in the United States 

Hsinchu, Taiwan, R.O.C., May 15, 2020 – TSMC (TWSE: 2330, NYSE: TSM) today announced its intention to build and operate an advanced semiconductor fab in the United States with the mutual understanding and commitment to support from the U.S. federal government and the State of Arizona. 

This facility, which will be built in Arizona, will utilize TSMC’s 5-nanometer technology for semiconductor wafer fabrication, have a 20,000 semiconductor wafer per month capacity, create over 1,600 high-tech professional jobs directly, and thousands of indirect jobs in the semiconductor ecosystem. Construction is planned to start in 2021 with production targeted to begin in 2024. TSMC’s total spending on this project, including capital expenditure, will be approximately US$12 billion from 2021 to 2029. This U.S. facility not only enables us to better support our customers and partners, it also gives us more opportunities to attract global talents. This project is of critical, strategic importance to a vibrant and competitive U.S. semiconductor ecosystem that enables leading U.S. companies to fabricate their cutting-edge semiconductor products within the United States and benefit from the proximity of a world-class semiconductor foundry and ecosystem. 

TSMC welcomes continued strong partnership with the U.S. administration and the State of Arizona on this project. This project will require significant capital and technology investments from TSMC. The strong investment climate in the United States, and its talented workforce make this and future investments in the U.S. attractive to TSMC. U.S. adoption of forward-looking investment policies to enable a globally competitive environment for a leading edge semiconductor technology operation in the U.S. will be crucial to the success of this project. It will also give us the confidence this and other future investments by TSMC and its supply chain companies will be successful.

 In the United States, TSMC currently operates a fab in Camas, Washington and design centers in both Austin, Texas and San Jose, California. The Arizona facility would be TSMC’s second manufacturing site in the United States

About TSMC 

TSMC pioneered the pure-play foundry business model when it was founded in 1987, and has been the world’s largest dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world. 

TSMC deployed 272 distinct process technologies, and manufactured 10,761 products for 499 customers in 2019 by providing broadest range of advanced, specialty and advanced packaging technology services. TSMC is the first foundry to provide 5-nanometer production capabilities, the most advanced semiconductor process technology available in the world. The Company is headquartered in Hsinchu, Taiwan

AtopTech No More?

EDA giant Synopsys sued AtopTech alleging patent infringement. After loosing battle AtopTech filed for bankruptcy.

ATopTech, Inc. Initiates Voluntary Chapter 11 Bankruptcy Protection Proceeding

It all started very promisingly.
EDA place-and-route startup ATopTech out of the gates with Broadcom win

But Synopsys doesn't like AtopTech using it's flagship PrimeTime report formats (and may be many more than this) in its tools. They decided to discuss the stuff in court and finally Judge/s gave the judgement in favor of Synopsys.
Synopsys, Inc. v. Atoptech, Inc, No. 3:2013cv02965 - Document 874 (N.D. Cal. 2016)

Read above document, it is pretty interesting, you won't find often VLSI in law schools and books, but here it is !

And now AtopTech website also doesn't work ! It shows some "Syntax Error", in typical style of EDA tool. Then how Aprisa can work !!

Thanks for reading !

Update 23rd Feb 2017:
Atoptech website is accessible now.


Is Qualcomm to Buy NXP Semiconductors?

Is Qualcomm to Buy NXP Semiconductors?

News reports are emerging with some details:


Brodcom Layoff in Server Team

Broadcom (Now part of Avago) seems to have laid -off it approximately 80 to 90 employees from server team affecting jobs in USA and India. Top management to bottom engineering level, all seems  to been affected by this move. Sometime back i heard rumors about Broadcom selling its Server business to unknown company. It is evident from the move that Avago doesn't believe R&D, just get the products out which can make money for it.

You may recall, since Avago acquired Broadcom in multi billion deal it has announced job cuts in large number to align its business priorities.

Intel to Layoff: 12000 Job Cut

Intel doing major shake-off, to layoff 12000 of its engineering force from PC business.
According to press release Intel is shifting its focus from PC business to IoT-Internet of Things, Data center, Memory and FPGAs, Connectivity business, Two-in-Ones, Gaming and Home Gateways.

Intel, Best of Luck !

Press Release

Intel Layoffs Are A Sign Of Poor Management

Western Digital Acquires SanDisk

Press release from Western Digital:

"New platform creates  greater scale and ability to deliver extensive portfolio of innovative products and technology

Combined business well-positioned  to capture growth and opportunities created by rapidly evolving storage industry

JV with Toshiba provides stable NAND supply at scale  through a time-tested business model and extends across NVM technologies such as 3D NAND"



Western Digital to buy SanDisk in $19 billion deal

SNUG India 2015 Paper: Tackling advanced DRCs and DPT violations using In-Design flow

I, along with co-author Ananda Veerasangaiah from Synopsys, presented a paper- "Tackling advanced DRCs and DPT violations using In-Design flow" in recently concluded SNUG India 2015, held at Bangalore. The paper can be downloaded below.

Tackling advanced DRCs and DPT violations using In-Design flow

SNUG India 2015 paper presentation;Photo courtesy: Ananda, Synopsys


Same paper is presented in this article.

Proceedings of SNUG India 2015 can be found in below link:
SNUG India 2015 Proceedings

Tackling advanced DRCs and DPT violations using In-Design flow

ABSTRACT



Sub-nano-meter technology gives more advantages to design community. However along with the advantages it also brings in lot of challenges along with it. one of them is DRC complacence. Starting from 20nm lower Metal layers has to be decomposed into two masks and this requirement gave raise to new set of DRC rules called Double Pattering Rules commonly known as DPT rules. Along with these rules, regular spacing and enclosure rules have increased both in numbers and complexity.
Routers can only get us to a reasonable closure on DRCs and due to complex DRCs and DPT violations, fixing DRC violations left by router is highly time consuming and manual process. DRC error fixing at 20nm and below nodes are very complicated and error prone. Manual fixing of DRCs will impact tape-out schedules. 

In this paper, we will talk about In-Design flow using Syopsys’ IC Validator and IC Compiler. This flow helped us in bringing down the DRC counts in an automated process. IC Validator brings the power of complete sign-off quality results as it takes foundry’s qualified sign-off runset and coupled with automatic DRC and DPT repair flow with IC Compiler. This seamless integration between IC Validator and IC Compiler makes stream-in and stream-out process redundant as this interface works completely inside Milkyway/IC Compiler environment.

With In-Design flow, designer can catch DRCs in IC Compiler environment and fix them without going through much of routing topology changes and with no timing impact. This boosts both productivity and tape-out schedules. In this paper we will be presenting impact of In-Design Auto DRC Repair flow on our designs and scope for improving the flow for increased productivity.

Training

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  • Job seekers can directly contact employer by either phone or email or whatever communication platform provided by employer.
  • Asic-soc blog hopes that this will benefit VLSI/Embedded community.
Thanks & Best Regards,
asic-soc blog

Environmental constraints

14.4. Environmental constraints

Both DRC and optimization constraints follow environmental constraints. Setting up of operating conditions and wire load model falls under environmental constraints.


Timing Constraints

14.3. Timing Constraints




These constraints specify clock related definitions which affect synthesis and timing analysis.