Companywise ASIC/VLSI Interview Questions

Below interview questions are contributed by ASIC_diehard (Thanks a lot !). Below questions are asked for senior position in Physical Design domain. The questions are also related to Static Timing Analysis and Synthesis. Answers to some questions are given as link. Remaining questions will be answered in coming blogs.

Common introductory questions every interviewer asks are:

• Discuss about the projects worked in the previous company.
• What are physical design flows, various activities you are involved?
• Design complexity, capacity, frequency, process technologies, block size you handled.

Intel

• Why power stripes routed in the top metal layers?

The resistivity of top metal layers are less and hence less IR drop is seen in power distribution network. If power stripes are routed in lower metal layers this will use good amount of lower routing resources and therefore it can create routing congestion.

• Why do you use alternate routing approach HVH/VHV (Horizontal-Vertical-Horizontal/ Vertical-Horizontal-Vertical)?

Answer:

This approach allows routability of the design and better usage of routing resources.

• What are several factors to improve propagation delay of standard cell?

Answer:

Improve the input transition to the cell under consideration by up sizing the driver.

Reduce the load seen by the cell under consideration, either by placement refinement or buffering.

If allowed increase the drive strength or replace with LVT (low threshold voltage) cell.

• How do you compute net delay (interconnect delay) / decode RC values present in tech file?
• What are various ways of timing optimization in synthesis tools?

Answer:

Logic optimization: buffer sizing, cell sizing, level adjustment, dummy buffering etc.

Less number of logics between Flip Flops speedup the design.

Optimize drive strength of the cell , so it is capable of driving more load and hence reducing the cell delay.

Better selection of design ware component (select timing optimized design ware components).

Use LVT (Low threshold voltage) and SVT (standard threshold voltage) cells if allowed.

• What would you do in order to not use certain cells from the library?

Answer:

Set don’t use attribute on those library cells.

• How delays are characterized using WLM (Wire Load Model)?

Answer:



For a given wireload model the delay are estimated based on the number of fanout of the cell driving the net.



Fanout vs net length is tabulated in WLMs.



Values of unit resistance R and unit capacitance C are given in technology file.



Net length varies based on the fanout number.



Once the net length is known delay can be calculated; Sometimes it is again tabulated.

• What are various techniques to resolve congestion/noise?

Answer:

Routing and placement congestion all depend upon the connectivity in the netlist , a better floor plan can reduce the congestion.

Noise can be reduced by optimizing the overlap of nets in the design.

• Let’s say there enough routing resources available, timing is fine, can you increase clock buffers in clock network? If so will there be any impact on other parameters?

Answer:

No. You should not increase clock buffers in the clock network. Increase in clock buffers cause more area , more power. When everything is fine why you want to touch clock tree??

• How do you optimize skew/insertion delays in CTS (Clock Tree Synthesis)?

Answer:

Better skew targets and insertion delay values provided while building the clocks.

Choose appropriate tree structure – either based on clock buffers or clock inverters or mix of clock buffers or clock inverters.

For multi clock domain, group the clocks while building the clock tree so that skew is balanced across the clocks. (Inter clock skew analysis).

• What are pros/cons of latch/FF (Flip Flop)?

Answer: Pros and cons of latch and flip flop

• How you go about fixing timing violations for latch- latch paths?
• As an engineer, let’s say your manager comes to you and asks for next project die size estimation/projection, giving data on RTL size, performance requirements. How do you go about the figuring out and come up with die size considering physical aspects?
• How will you design inserting voltage island scheme between macro pins crossing core and are at different power wells? What is the optimal resource solution?
• What are various formal verification issues you faced and how did you resolve?
• How do you calculate maximum frequency given setup, hold, clock and clock skew?
• What are effects of metastability?

Answer: Metastability

• Consider a timing path crossing from fast clock domain to slow clock domain. How do you design synchronizer circuit without knowing the source clock frequency?
• How to solve cross clock timing path?
• How to determine the depth of FIFO/ size of the FIFO?

Answer: FIFO Depth

STmicroelectronics

• What are the challenges you faced in place and route, FV (Formal Verification), ECO (Engineering Change Order) areas?
• How long the design cycle for your designs?
• What part are your areas of interest in physical design?
• Explain ECO (Engineering Change Order) methodology.
• Explain CTS (Clock Tree Synthesis) flow.

Answer: Clock Tree Synthesis

• What kind of routing issues you faced?
• How does STA (Static Timing Analysis) in OCV (On Chip Variation) conditions done? How do you set OCV (On Chip Variation) in IC compiler? How is timing correlation done before and after place and route?

Answer: Process-Voltage-Temperature (PVT) Variations and Static Timing Analysis (STA)

• If there are too many pins of the logic cells in one place within core, what kind of issues would you face and how will you resolve?
• Define hash/ @array in perl.
• Using TCL (Tool Command Language, Tickle) how do you set variables?
• What is ICC (IC Compiler) command for setting derate factor/ command to perform physical synthesis?
• What are nanoroute options for search and repair?
• What were your design skew/insertion delay targets?
• How is IR drop analysis done? What are various statistics available in reports?
• Explain pin density/ cell density issues, hotspots?
• How will you relate routing grid with manufacturing grid and judge if the routing grid is set correctly?
• What is the command for setting multi cycle path?
• If hold violation exists in design, is it OK to sign off design? If not, why?

Texas Instruments (TI)

• How are timing constraints developed?
• Explain timing closure flow/methodology/issues/fixes.
• Explain SDF (Standard Delay Format) back annotation/ SPEF (Standard Parasitic Exchange Format) timing correlation flow.
• Given a timing path in multi-mode multi-corner, how is STA (Static Timing Analysis) performed in order to meet timing in both modes and corners, how are PVT (Process-Voltage-Temperature)/derate factors decided and set in the Primetime flow?
• With respect to clock gate, what are various issues you faced at various stages in the physical design flow?
• What are synthesis strategies to optimize timing?
• Explain ECO (Engineering Change Order) implementation flow. Given post routed database and functional fixes, how will you take it to implement ECO (Engineering Change Order) and what physical and functional checks you need to perform?

Qualcomm

• In building the timing constraints, do you need to constrain all IO (Input-Output) ports?
• Can a single port have multi-clocked? How do you set delays for such ports?
• How is scan DEF (Design Exchange Format) generated?
• What is purpose of lockup latch in scan chain?
• Explain short circuit current.

Answer: Short Circuit Power

• What are pros/cons of using low Vt, high Vt cells?

Answer:

Multi Threshold Voltage Technique

Issues With Multi Height Cell Placement in Multi Vt Flow

• How do you set inter clock uncertainty?

Answer:

set_clock_uncertainty –from clock1 -to clock2

• In DC (Design Compiler), how do you constrain clocks, IO (Input-Output) ports, maxcap, max tran?
• What are differences in clock constraints from pre CTS (Clock Tree Synthesis) to post CTS (Clock Tree Synthesis)?

Answer:

Difference in clock uncertainty values; Clocks are propagated in post CTS.

In post CTS clock latency constraint is modified to model clock jitter.

• How is clock gating done?

Answer: Clock Gating

• What constraints you add in CTS (Clock Tree Synthesis) for clock gates?

Answer:

Make the clock gating cells as through pins.

• What is trade off between dynamic power (current) and leakage power (current)?

Answer:

Leakage Power Trends

Dynamic Power

• How do you reduce standby (leakage) power?

Answer: Low Power Design Techniques

• Explain top level pin placement flow? What are parameters to decide?
• Given block level netlists, timing constraints, libraries, macro LEFs (Layout Exchange Format/Library Exchange Format), how will you start floor planning?
• With net length of 1000um how will you compute RC values, using equations/tech file info?
• What do noise reports represent?
• What does glitch reports contain?
• What are CTS (Clock Tree Synthesis) steps in IC compiler?
• What do clock constraints file contain?
• How to analyze clock tree reports?
• What do IR drop Voltagestorm reports represent?
• Where /when do you use DCAP (Decoupling Capacitor) cells?
• What are various power reduction techniques?

Answer: Low Power Design Techniques

Hughes Networks

• What is setup/hold? What are setup and hold time impacts on timing? How will you fix setup and hold violations?
• Explain function of Muxed FF (Multiplexed Flip Flop) /scan FF (Scal Flip Flop).
• What are tested in DFT (Design for Testability)?
• In equivalence checking, how do you handle scanen signal?
• In terms of CMOS (Complimentary Metal Oxide Semiconductor), explain physical parameters that affect the propagation delay?
• What are power dissipation components? How do you reduce them?

Answer:

Short Circuit Power

Leakage Power Trends

Dynamic Power

Low Power Design Techniques

• How delay affected by PVT (Process-Voltage-Temperature)?

Answer: Process-Voltage-Temperature (PVT) Variations and Static Timing Analysis (STA)

• Why is power signal routed in top metal layers?

Avago Technologies (former HP group)

• How do you minimize clock skew/ balance clock tree?
• Given 11 minterms and asked to derive the logic function.
• Given C1= 10pf, C2=1pf connected in series with a switch in between, at t=0 switch is open and one end having 5v and other end zero voltage; compute the voltage across C2 when the switch is closed?
• Explain the modes of operation of CMOS (Complimentary Metal Oxide Semiconductor) inverter? Show IO (Input-Output) characteristics curve.
• Implement a ring oscillator.
• How to slow down ring oscillator?

Hynix Semiconductor

• How do you optimize power at various stages in the physical design flow?
• What timing optimization strategies you employ in pre-layout /post-layout stages?
• What are process technology challenges in physical design?
• Design divide by 2, divide by 3, and divide by 1.5 counters. Draw timing diagrams.
• What are multi-cycle paths, false paths? How to resolve multi-cycle and false paths?
• Given a flop to flop path with combo delay in between and output of the second flop fed back to combo logic. Which path is fastest path to have hold violation and how will you resolve?
• What are RTL (Register Transfer Level) coding styles to adapt to yield optimal backend design?
• Draw timing diagrams to represent the propagation delay, set up, hold, recovery, removal, minimum pulse width.

About Contributor

ASIC_diehard has more than 5 years of experience in physical design, timing, netlist to GDS flows of Integrated Circuit development. ASIC_diehard's fields of interest are backend design, place and route, timing closure, process technologies.

Readers are encouraged to discuss answers to these questions. Just click on the 'post a comment' option below and put your comments there. Alternatively you can send your answers/discussions to my mail id: shavakmm@gmail.com

What is the difference between soft macro and hard macro?

• What is the difference between hard macro, firm macro and soft macro?

or

• What are IPs?

• Hard macro, firm macro and soft macro are all known as IP (Intellectual property). They are optimized for power, area and performance. They can be purchased and used in your ASIC or FPGA design implementation flow. Soft macro is flexible for all type of ASIC implementation. Hard macro can be used in pure ASIC design flow, not in FPGA flow. Before bying any IP it is very important to evaluate its advantages and disadvantages over each other, hardware compatibility such as I/O standards with your design blocks, reusability for other designs.

Soft macros

• Soft macros are in synthesizable RTL.

• Soft macros are more flexible than firm or hard macros.

• Soft macros are not specific to any manufacturing process.

• Soft macros have the disadvantage of being somewhat unpredictable in terms of performance, timing, area, or power.

• Soft macros carry greater IP protection risks because RTL source code is more portable and therefore, less easily protected than either a netlist or physical layout data.

• From the physical design perspective, soft macro is any cell that has been placed and routed in a placement and routing tool such as Astro. (This is the definition given in Astro Rail user manual !)

• Soft macros are editable and can contain standard cells, hard macros, or other soft macros.

Firm macros

• Firm macros are in netlist format.

• Firm macros are optimized for performance/area/power using a specific fabrication technology.

• Firm macros are more flexible and portable than hard macros.

• Firm macros are predictive of performance and area than soft macros.

Hard macro

• Hard macros are generally in the form of hardware IPs (or we termed it as hardwre IPs !).

• Hard macos are targeted for specific IC manufacturing technology.

• Hard macros are block level designs which are silicon tested and proved.

• Hard macros have been optimized for power or area or timing.

• In physical design you can only access pins of hard macros unlike soft macros which allows us to manipulate in different way.

• You have freedom to move, rotate, flip but you can't touch anything inside hard macros.

• Very common example of hard macro is memory. It can be any design which carries dedicated single functionality (in general).. for example it can be a MP4 decoder.

• Be aware of features and characteristics of hard macro before you use it in your design... other than power, timing and area you also should know pin properties like sync pin, I/O standards etc

• LEF, GDS2 file format allows easy usage of macros in different tools.

From the physical design (backend) perspective:

• Hard macro is a block that is generated in a methodology other than place and route (i.e. using full custom design methodology) and is brought into the physical design database (eg. Milkyway in Synopsys; Volcano in Magma) as a GDS2 file.

• Here is one article published in embedded magazine about IPs. Click here to read.

Synthesis and placement of macros in modern SoC designs are challenging. EDA tools employ different algorithms accomplish this task along with the target of power and area. There are several research papers available on these subjects. Some of them can be downloaded from the given link below.

• "Hard Macro Placement in Complex SoC Design" - view and read article from soccentral

• "Hard Macro Placement in Complex SoC Design" - download white paper

IEEE/Univerity research papers

• "Local Search for Final Placement in VLSI Design" - download

• "Consistent Placement of Macro-Blocks Using Floorplanning and standard cell placement" - download

• "A Timing-Driven Soft-Macro Placement And Resynthesis Method In Interaction with Chip Floorplanning" - download

What is the difference between FPGA and CPLD?

FPGA-Field Programmable Gate Array and CPLD-Complex Programmable Logic Device-- both are programmable logic devices made by the same companies with different characteristics.

• "A Complex Programmable Logic Device (CPLD) is a Programmable Logic Device with complexity between that of PALs (Programmable Array Logic) and FPGAs, and architectural features of both. The building block of a CPLD is the macro cell, which contains logic implementing disjunctive normal form expressions and more specialized logic operations".

• This is what Wiki defines.....!!

• Click here to see what else wiki has to say about it !

Architecture

• Granularity is the biggest difference between CPLD and FPGA.

• FPGA are "fine-grain" devices. That means that they contain hundreds of (up to 100000) of tiny blocks (called as LUT or CLBs etc) of logic with flip-flops, combinational logic and memories.FPGAs offer much higher complexity, up to 150,000 flip-flops and large number of gates available.

• CPLDs typically have the equivalent of thousands of logic gates, allowing implementation of moderately complicated data processing devices. PALs typically have a few hundred gate equivalents at most, while FPGAs typically range from tens of thousands to several million.

• CPLD are "coarse-grain" devices. They contain relatively few (a few 100's max) large blocks of logic with flip-flops and combinational logic. CPLDs based on AND-OR structure.

• CPLD's have a register with associated logic (AND/OR matrix). CPLD's are mostly implemented in control applications and FPGA's in datapath applications. Because of this course grained architecture, the timing is very fixed in CPLDs.

• FPGA are RAM based. They need to be "downloaded" (configured) at each power-up. CPLD are EEPROM based. They are active at power-up i.e. as long as they've been programmed at least once.

• FPGA needs boot ROM but CPLD does not. In some systems you might not have enough time to boot up FPGA then you need CPLD+FPGA.

• Generally, the CPLD devices are not volatile, because they contain flash or erasable ROM memory in all the cases. The FPGA are volatile in many cases and hence they need a configuration memory for working. There are some FPGAs now which are nonvolatile. This distinction is rapidly becoming less relevant, as several of the latest FPGA products also offer models with embedded configuration memory.

• The characteristic of non-volatility makes the CPLD the device of choice in modern digital designs to perform 'boot loader' functions before handing over control to other devices not having this capability. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory.

• Because of coarse-grain architecture, one block of logic can hold a big equation and hence CPLD have a faster input-to-output timings than FPGA.

• Click here to read one good article.

Features

• FPGA have special routing resources to implement binary counters,arithmetic functions like adders, comparators and RAM. CPLD don't have special features like this.

• FPGA can contain very large digital designs, while CPLD can contain small designs only.The limited complexity (<500>

• Speed: CPLDs offer a single-chip solution with fast pin-to-pin delays, even for wide input functions. Use CPLDs for small designs, where "instant-on", fast and wide decoding, ultra-low idle power consumption, and design security are important (e.g., in battery-operated equipment).

• Security: In CPLD once programmed, the design can be locked and thus made secure. Since the configuration bitstream must be reloaded every time power is re-applied, design security in FPGA is an issue.

• Power: The high static (idle) power consumption prohibits use of CPLD in battery-operated equipment. FPGA idle power consumption is reasonably low, although it is sharply increasing in the newest families.

• Design flexibility: FPGAs offer more logic flexibility and more sophisticated system features than CPLDs: clock management, on-chip RAM, DSP functions, (multipliers), and even on-chip microprocessors and Multi-Gigabit Transceivers.These benefits and opportunities of dynamic reconfiguration, even in the end-user system, are an important advantage.

• Use FPGAs for larger and more complex designs.

Click here to read what Xilinx has to say about it.

• FPGA is suited for timing circuit becauce they have more registers , but CPLD is suited for control circuit because they have more combinational circuit. At the same time, If you synthesis the same code for FPGA for many times, you will find out that each timing report is different. But it is different in CPLD synthesis, you can get the same result.

As CPLDs and FPGAs become more advanced the differences between the two device types will continue to blur. While this trend may appear to make the two types more difficult to keep apart, the architectural advantage of CPLDs combining low cost, non-volatile configuration, and macro cells with predictable timing characteristics will likely be sufficient to maintain a product differentiation for the foreseeable future.

• There are people who discuss about this. Click here to listen them.

• Finally here is one pdf document whcih is downloadable: "Architecture of FPGAs and CPLDs: A Tutorial" Download

Hoping that information and references helps you ....... comments and further references are welcome !

VLSI Interview Questions...... CMOS

VLSI/ASIC/CMOS/Digital Interview Questions

Click here to read more VLSI/ASIC/CMOS/Digital design interview questions and answers !

1. What happens if Vds is increased over saturation?
Ans:Pinch off
2. In the I-V characteristics curve, why is the saturation curve flat or constant?
Ans: no consideration of channel length modulation
3. What happens if a resistor is added in series with the drain in a mos transistor?
4. What are the different regions of operation in a mos transistor?
5. What are the effects of the output characteristics for a change in the beta (β) value?
6. What is the effect of body bias?
7. What is hot electron effect and how can it be eliminated?
8. What is latchup problem and how can it be eliminated?
9. What is channel length modulation?
10. What is the effect of temperature on threshold voltage?
11. What is the effect of temperature on mobility? What is the effect of gate voltage on mobility?
12. What are the different types of scaling?
13. What is stage ratio?
14. What is charge sharing on a bus?
15. What is electron migration and how can it be eliminated?
16. Can both pmos and nmos transistors pass good 1 and good 0? Explain.
17. Why is only nmos used in pass transistor logic?
18. What are the different methodologies used to reduce the charge sharing in dynamic logic?
19. What are setup and hold time violations? How can they be eliminated?
20. Explain the operation of basic sram and dram.
21. Of Read and Write operations, which ones take more time? Explain.
22. What is meant by clock race?
23. What is meant by single phase and double phase clocking?
24. If given a choice between NAND and NOR gates, which one would you pick?
Explain.
25. What are stuck-at faults?
26. What is meant by ATPG?
27. What is meant by noise margin in an inverter? How can you overcome it?
28. Why is size of pmos transistor chosen to be close to three times of an nmos transistor?
29. Explain the origin of the various capacitances in the mos transistor and the physical reasoning behind it.
30. Why should the number of CMOS transistors that are connected in series be reduced?
31. What is charge sharing between bus and memory element?
32. What is crosstalk and how can it be avoided?
33. Two inverters are connected in series. The widths of pmos and nmos transistors of the second inverter are 100 and 50 respectively. If the fan-out is assumed to be 3, what would be the widths of the transistors in the first inverter?
34. In the above situation, what would be the widths of the transistors if the first inverter is replaced by NAND and NOR gates?
35. What is the difference between a latch and flip-flop? Give examples of the applications of each.
36. Realize an XOR gate using NAND gate.
37. What are the advantages and disadvantages of Bi-CMOS process?
38. Draw an XOR gate with using minimal number of transistors and explain the operation.
39. What are the critical parameters in a latch and flip-flop?
40. What is the significance of sense amplifier in an SRAM?
41. Explain Domino logic.
42. What are the differences between PALs, PLAs, FPGAs, ASICs and PLDs?
43. What are the advantages of depletion mode devices over the enhancement mode devices?
44. How can the rise and fall times in an inverter be equated?
45. What is meant by leakage current?
46. Realize an OR gate using NAND gate.
47. Realize an NAND gate using a 2:1 multiplexer.
48. Realize an NOR gate using a 2:1 multiplexer.
49. Draw the layout of a simple inverter.
50. What are the substrates of pmos and nmos transistors connected to and explain the results if the connections are interchanged with the other.
51. What are repeaters in VLSI design?
52. What is meant by tunneling problem?
53. What is meant by negative biased instability and how can it be avoided?
54. What is Elmore delay algorithm?
55. What are false and multi cycle paths?
56. What is meant by metastability?
57. What are the various factors that need to be considered while choosing a technology library for a design?
58. What is meant by clock skew and how can it be avoided?
59. When stated as 0.13μm CMOS technology, what does 0.13 represent?
60. What is the effect of Vdd on delay?
61. What are the various limitations in changing the voltage for less delay?
62. What is the difference between testing and verification?
63. While trying to drive a huge load, driver circuits are designed with number of stages with a gradual increase in sizes. Why is this done so? What not use just one big driver gate?
64. What is the effect of increase in the number of contacts and vias in the interconnect layers?
65. How does the resistance of the metal layer vary with increasing thickness and increasing length?
66. What is the effect of delay, rise and fall times with increase in load capacitance?
67. In a simple inverter circuit, if the pmos in the Pull-Up Network is replaced by an nmos and if the nmos in the Pull-Down Network is replaced by a pmos transistor, will the design work as an non-inverting buffer? Justify your answer.
68. What is mobility of electrons?
69. What is mobility of holes?