Companywise ASIC/VLSI Interview Questions

Below interview questions are contributed by ASIC_diehard (Thanks a lot !). Below questions are asked for senior position in Physical Design domain. The questions are also related to Static Timing Analysis and Synthesis. Answers to some questions are given as link. Remaining questions will be answered in coming blogs.

Common introductory questions every interviewer asks are:

• Discuss about the projects worked in the previous company.
• What are physical design flows, various activities you are involved?
• Design complexity, capacity, frequency, process technologies, block size you handled.

Intel

• Why power stripes routed in the top metal layers?

The resistivity of top metal layers are less and hence less IR drop is seen in power distribution network. If power stripes are routed in lower metal layers this will use good amount of lower routing resources and therefore it can create routing congestion.

• Why do you use alternate routing approach HVH/VHV (Horizontal-Vertical-Horizontal/ Vertical-Horizontal-Vertical)?

Answer:

This approach allows routability of the design and better usage of routing resources.

• What are several factors to improve propagation delay of standard cell?

Answer:

Improve the input transition to the cell under consideration by up sizing the driver.

Reduce the load seen by the cell under consideration, either by placement refinement or buffering.

If allowed increase the drive strength or replace with LVT (low threshold voltage) cell.

• How do you compute net delay (interconnect delay) / decode RC values present in tech file?
• What are various ways of timing optimization in synthesis tools?

Answer:

Logic optimization: buffer sizing, cell sizing, level adjustment, dummy buffering etc.

Less number of logics between Flip Flops speedup the design.

Optimize drive strength of the cell , so it is capable of driving more load and hence reducing the cell delay.

Better selection of design ware component (select timing optimized design ware components).

Use LVT (Low threshold voltage) and SVT (standard threshold voltage) cells if allowed.

• What would you do in order to not use certain cells from the library?

Answer:

Set don’t use attribute on those library cells.

• How delays are characterized using WLM (Wire Load Model)?

Answer:



For a given wireload model the delay are estimated based on the number of fanout of the cell driving the net.



Fanout vs net length is tabulated in WLMs.



Values of unit resistance R and unit capacitance C are given in technology file.



Net length varies based on the fanout number.



Once the net length is known delay can be calculated; Sometimes it is again tabulated.

• What are various techniques to resolve congestion/noise?

Answer:

Routing and placement congestion all depend upon the connectivity in the netlist , a better floor plan can reduce the congestion.

Noise can be reduced by optimizing the overlap of nets in the design.

• Let’s say there enough routing resources available, timing is fine, can you increase clock buffers in clock network? If so will there be any impact on other parameters?

Answer:

No. You should not increase clock buffers in the clock network. Increase in clock buffers cause more area , more power. When everything is fine why you want to touch clock tree??

• How do you optimize skew/insertion delays in CTS (Clock Tree Synthesis)?

Answer:

Better skew targets and insertion delay values provided while building the clocks.

Choose appropriate tree structure – either based on clock buffers or clock inverters or mix of clock buffers or clock inverters.

For multi clock domain, group the clocks while building the clock tree so that skew is balanced across the clocks. (Inter clock skew analysis).

• What are pros/cons of latch/FF (Flip Flop)?

Answer: Pros and cons of latch and flip flop

• How you go about fixing timing violations for latch- latch paths?
• As an engineer, let’s say your manager comes to you and asks for next project die size estimation/projection, giving data on RTL size, performance requirements. How do you go about the figuring out and come up with die size considering physical aspects?
• How will you design inserting voltage island scheme between macro pins crossing core and are at different power wells? What is the optimal resource solution?
• What are various formal verification issues you faced and how did you resolve?
• How do you calculate maximum frequency given setup, hold, clock and clock skew?
• What are effects of metastability?

Answer: Metastability

• Consider a timing path crossing from fast clock domain to slow clock domain. How do you design synchronizer circuit without knowing the source clock frequency?
• How to solve cross clock timing path?
• How to determine the depth of FIFO/ size of the FIFO?

Answer: FIFO Depth

STmicroelectronics

• What are the challenges you faced in place and route, FV (Formal Verification), ECO (Engineering Change Order) areas?
• How long the design cycle for your designs?
• What part are your areas of interest in physical design?
• Explain ECO (Engineering Change Order) methodology.
• Explain CTS (Clock Tree Synthesis) flow.

Answer: Clock Tree Synthesis

• What kind of routing issues you faced?
• How does STA (Static Timing Analysis) in OCV (On Chip Variation) conditions done? How do you set OCV (On Chip Variation) in IC compiler? How is timing correlation done before and after place and route?

Answer: Process-Voltage-Temperature (PVT) Variations and Static Timing Analysis (STA)

• If there are too many pins of the logic cells in one place within core, what kind of issues would you face and how will you resolve?
• Define hash/ @array in perl.
• Using TCL (Tool Command Language, Tickle) how do you set variables?
• What is ICC (IC Compiler) command for setting derate factor/ command to perform physical synthesis?
• What are nanoroute options for search and repair?
• What were your design skew/insertion delay targets?
• How is IR drop analysis done? What are various statistics available in reports?
• Explain pin density/ cell density issues, hotspots?
• How will you relate routing grid with manufacturing grid and judge if the routing grid is set correctly?
• What is the command for setting multi cycle path?
• If hold violation exists in design, is it OK to sign off design? If not, why?

Texas Instruments (TI)

• How are timing constraints developed?
• Explain timing closure flow/methodology/issues/fixes.
• Explain SDF (Standard Delay Format) back annotation/ SPEF (Standard Parasitic Exchange Format) timing correlation flow.
• Given a timing path in multi-mode multi-corner, how is STA (Static Timing Analysis) performed in order to meet timing in both modes and corners, how are PVT (Process-Voltage-Temperature)/derate factors decided and set in the Primetime flow?
• With respect to clock gate, what are various issues you faced at various stages in the physical design flow?
• What are synthesis strategies to optimize timing?
• Explain ECO (Engineering Change Order) implementation flow. Given post routed database and functional fixes, how will you take it to implement ECO (Engineering Change Order) and what physical and functional checks you need to perform?

Qualcomm

• In building the timing constraints, do you need to constrain all IO (Input-Output) ports?
• Can a single port have multi-clocked? How do you set delays for such ports?
• How is scan DEF (Design Exchange Format) generated?
• What is purpose of lockup latch in scan chain?
• Explain short circuit current.

Answer: Short Circuit Power

• What are pros/cons of using low Vt, high Vt cells?

Answer:

Multi Threshold Voltage Technique

Issues With Multi Height Cell Placement in Multi Vt Flow

• How do you set inter clock uncertainty?

Answer:

set_clock_uncertainty –from clock1 -to clock2

• In DC (Design Compiler), how do you constrain clocks, IO (Input-Output) ports, maxcap, max tran?
• What are differences in clock constraints from pre CTS (Clock Tree Synthesis) to post CTS (Clock Tree Synthesis)?

Answer:

Difference in clock uncertainty values; Clocks are propagated in post CTS.

In post CTS clock latency constraint is modified to model clock jitter.

• How is clock gating done?

Answer: Clock Gating

• What constraints you add in CTS (Clock Tree Synthesis) for clock gates?

Answer:

Make the clock gating cells as through pins.

• What is trade off between dynamic power (current) and leakage power (current)?

Answer:

Leakage Power Trends

Dynamic Power

• How do you reduce standby (leakage) power?

Answer: Low Power Design Techniques

• Explain top level pin placement flow? What are parameters to decide?
• Given block level netlists, timing constraints, libraries, macro LEFs (Layout Exchange Format/Library Exchange Format), how will you start floor planning?
• With net length of 1000um how will you compute RC values, using equations/tech file info?
• What do noise reports represent?
• What does glitch reports contain?
• What are CTS (Clock Tree Synthesis) steps in IC compiler?
• What do clock constraints file contain?
• How to analyze clock tree reports?
• What do IR drop Voltagestorm reports represent?
• Where /when do you use DCAP (Decoupling Capacitor) cells?
• What are various power reduction techniques?

Answer: Low Power Design Techniques

Hughes Networks

• What is setup/hold? What are setup and hold time impacts on timing? How will you fix setup and hold violations?
• Explain function of Muxed FF (Multiplexed Flip Flop) /scan FF (Scal Flip Flop).
• What are tested in DFT (Design for Testability)?
• In equivalence checking, how do you handle scanen signal?
• In terms of CMOS (Complimentary Metal Oxide Semiconductor), explain physical parameters that affect the propagation delay?
• What are power dissipation components? How do you reduce them?

Answer:

Short Circuit Power

Leakage Power Trends

Dynamic Power

Low Power Design Techniques

• How delay affected by PVT (Process-Voltage-Temperature)?

Answer: Process-Voltage-Temperature (PVT) Variations and Static Timing Analysis (STA)

• Why is power signal routed in top metal layers?

Avago Technologies (former HP group)

• How do you minimize clock skew/ balance clock tree?
• Given 11 minterms and asked to derive the logic function.
• Given C1= 10pf, C2=1pf connected in series with a switch in between, at t=0 switch is open and one end having 5v and other end zero voltage; compute the voltage across C2 when the switch is closed?
• Explain the modes of operation of CMOS (Complimentary Metal Oxide Semiconductor) inverter? Show IO (Input-Output) characteristics curve.
• Implement a ring oscillator.
• How to slow down ring oscillator?

Hynix Semiconductor

• How do you optimize power at various stages in the physical design flow?
• What timing optimization strategies you employ in pre-layout /post-layout stages?
• What are process technology challenges in physical design?
• Design divide by 2, divide by 3, and divide by 1.5 counters. Draw timing diagrams.
• What are multi-cycle paths, false paths? How to resolve multi-cycle and false paths?
• Given a flop to flop path with combo delay in between and output of the second flop fed back to combo logic. Which path is fastest path to have hold violation and how will you resolve?
• What are RTL (Register Transfer Level) coding styles to adapt to yield optimal backend design?
• Draw timing diagrams to represent the propagation delay, set up, hold, recovery, removal, minimum pulse width.

About Contributor

ASIC_diehard has more than 5 years of experience in physical design, timing, netlist to GDS flows of Integrated Circuit development. ASIC_diehard's fields of interest are backend design, place and route, timing closure, process technologies.

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