Environmental constraints

14.4. Environmental constraints

Both DRC and optimization constraints follow environmental constraints. Setting up of operating conditions and wire load model falls under environmental constraints.

Timing Constraints

14.3. Timing Constraints

These constraints specify clock related definitions which affect synthesis and timing analysis.

Optimization constraints

14.2 Optimization constraints

Three types of optimizations are possible-area, power and timing. We have optimization constraints related to all these. Synthesis tools assign higher priority to timing constraints over area and power constraints.

Design Objects

1.    Design Objects

Design objects which are regularly used w.r.to design are design is explained below.

Wire load models for synthesis

9.1. Wire load models for synthesis

Wire load modeling allows us to estimate the effect of wire length and fanout on the resistance, capacitance, and area of nets. Synthesizer uses these physical values to calculate wire delays and circuit speeds. Semiconductor vendors develop wire load models, based on statistical information specific to the vendors’ process. The models include coefficients for area, capacitance, and resistance per unit length, and a fanout-to-length table for estimating net lengths (the number of fanouts determines a nominal length).

Wire load models

1.    Wire load models

Extraction data from already routed designs are used to build a lookup table known as the wire load model (WLM). WLM is based on the statistical estimates of R and C based on “Net Fan-out”.

Operating Condition: Operating Temperature Variation

8.3. Operating Temperature Variation

Temperature variation is unavoidable in the everyday operation of a design. Effects on performance caused by temperature fluctuations are most often handled as linear scaling effects, but some submicron silicon processes require nonlinear calculations.

Operating Condition: Supply Voltage Variation

8.2. Supply Voltage Variation

The design’s supply voltage can vary from the established ideal value during day-to-day operation. Often a complex calculation (using a shift in threshold voltages) is employed, but a simple linear scaling factor is also used for logic-level performance calculations.

Operating Condition: Process Variation

8.1. Process Variation

This variation accounts for deviations in the semiconductor fabrication process. Usually process variation is treated as a percentage variation in the performance calculation. Variations in the process parameters can be impurity concentration densities, oxide thicknesses and diffusion depths. These are caused bye non uniform conditions during depositions and/or during diffusions of the impurities. This introduces variations in the sheet resistance and transistor parameters such as threshold voltage. Variations are in the dimensions of the devices, mainly resulting from the limited resolution of the photolithographic process. This causes (W/L) variations in MOS transistors.

Operating conditions

1.     Operating conditions

Sources of variation in performance of a chip are due to:

Ø  Process variation (P)

Ø  Supply voltage (V)

Ø  Operating Temperature (T)

.lib: Cell description

7.2.4. Cell description

A cell description in the logic library contains variety of attributes describibing the function, timing, power and any other related information of the cell.

.lib: Wire Load Models

7.2.3.3. Wire Load Models

Wire load models contain informations that synthnesis tool utilizes to estimate interconnect wiring delays during logic synthesis phase of the design. Logic library includes several models approarpriate to different sizes of the design.

.lib: Operating Conditions:

7.2.3.2. Operating Conditions:

This section models the environmental variations of IC. These are known as Process, Voltage, and temperature variations. In short it is called PVT.

 

A set of values of PVT is known as operating condition. A logic library is characterised for one set of operating condition. Generally there are different libraries specific to different operating condition. There are three operating conditions very commonly used in ASIC synthesis and implementation. Based on the affect on cell delay due to the variation in PVT these classifications are made.

They are:

Ø  worst (also called ‘max’ or ‘slow’)à library in which cells are characterised for maximum delay

Ø  best(also called ‘min’ or ‘fast’)àlibrary in which cells are characterised for minimum delay

Ø  nominal(also called ‘typical’ or ‘normal’)àlibrary in which cells are characterised for typical delay

Eg.:

  /* Operation Conditions */

  nom_process                     : 1.00;

  nom_temperature                 : 125.00;

  nom_voltage                     : 0.95;

 

  voltage_map (VDD,0.95);

  voltage_map (VSS,0.00);

 

  define(process_corner, operating_conditions, string);

  operating_conditions (slow) {

    process_corner : "SlowSlow";

    process       : 1.00;

    voltage       : 0.95;

    temperature   : 125.00;

    tree_type     : balanced_tree;

  }

  default_operating_conditions : slow;

.lib: Environment Description

7.2.3. Environment Description

7.2.3.1. Scaling Factors:

The scaling factors (also called as K-factors) are multipliers that provide flexibility for derating the delay values based on PVT.  If PVT changes by a particular value then how to calculate parameter like cell delay or net delay? using these K-factors that can be accomplished.

Inputs and output from ASIC synthesis flow

6.2. Inputs and output from ASIC synthesis flow

Outcome of Synthesis is Gate level netlist which is again in Standard Verilog format. Netlists can be simulated as well which we call as Gate Level Simulation.

6.2.1. Register Transfer Level (RTL) Representation

RTL is the functional specification of the design to logic synthsis which is represented by HDLs.

Ø  Register: Storage element like F-F, latches

Ø  Transfer: Transfer data between input, output and register using combinational logic.

Ø  Level: Level of Abstraction modeled using HDL.

6.2.2. Constraints

The major objective of the logic synthesis is to meet the optimization constraints specified by the designer. Timing, area and power targets are the optimization constraints.

Ø  Timing Constraints: The synthesis tool tries to meet the setup and hold timing constraints on the sequential logic in the design.

Ø  Area constraints: Area constraints specifies maximum area for a design.

Ø  Power Constraints: Power constraints specifies the maximum power consumption for the design.

 

6.2.3. Target Library

 Target library is standard cell library corresponding to a particular technology node (eg. 45nm). This is a collection of combinational logic gates and sequential logic elements which are used to convert HDL to gate level netlist.

 

If logic synthesis is carried ou for FPGAs then HDL description is translated and mapped to LUTs, flip-flops and block RAMs.  For FPGA implementation separate synthesis tool is required. ASIC synthesis tool can’t synthesize the HDL into FPGA omplemtable netlist.

 

A clean technology independent HDL description of design can be synthesized to any technology node. This can also be targeted for FPGA implementations.

 

ASIC Synthesis: Synthesis definition, goals

1.     ASIC Synthesis

6.1. Synthesis definition, goals

Synthesis is the process of transforming your HDL design into a gate-level netlist, given all the specified constraints and optimization settings.

Logic synthesis is the process of translating and mapping RTL code written in HDL (such as Verilog or VHDL ) into technology specific gate  level representation.

 

There are 3 steps in Synthesis:

Ø  Translation: RTL code is translated to technolohgy independent representation. The converted logic is available in boolean equation form.

Ø  Optimization: Boolean equation is optimized using SoP or PoS optimization methods.

Ø  Technology mapping:  Technology independent boolean logic equations are mapped to technology dependant library logic gates based on design constraints, library of available technology gates.  This produces optimized gate level representation which is generally represented in Verilog.

 

 

Then the gate level circuit generated is logically optimized to meet the targets or goals set as per the user constraints. The clock frequency target is the number one goal that has to be met by the synthesis operation.