Environmental constraints

14.4. Environmental constraints

Both DRC and optimization constraints follow environmental constraints. Setting up of operating conditions and wire load model falls under environmental constraints.

Timing Constraints

14.3. Timing Constraints

These constraints specify clock related definitions which affect synthesis and timing analysis.

Optimization constraints

14.2 Optimization constraints

Three types of optimizations are possible-area, power and timing. We have optimization constraints related to all these. Synthesis tools assign higher priority to timing constraints over area and power constraints.

Logical DRC constraints

14.1. Logical DRC constraints

DRC constraints exist in library. DRC constraints can’t be relaxed. They can be chosen from library. These constraints are imposed upon the design by requirements specified in the target technology library. This presides over optimization constraints to realize a functional design.

Constraints: Clock, Logical DRC, Area, Power

14.    Constraints: Clock, Logical DRC, Area, Power

 

Design constraints are generally specified in “Synopsys Design Constraints” (SDC) form. SDC is very widely used and industry accepted standard for specifying design constraints.

Three types of constraints can be set for the design. They are:

1) Logical DRC constraints
2) Optimization constraints
3) Environmental constraints.