Optimization constraints

14.2 Optimization constraints

Three types of optimizations are possible-area, power and timing. We have optimization constraints related to all these. Synthesis tools assign higher priority to timing constraints over area and power constraints.

Logical DRC constraints

14.1. Logical DRC constraints

DRC constraints exist in library. DRC constraints can’t be relaxed. They can be chosen from library. These constraints are imposed upon the design by requirements specified in the target technology library. This presides over optimization constraints to realize a functional design.

Design Objects

1.    Design Objects

Design objects which are regularly used w.r.to design are design is explained below.

Wire load models for synthesis

9.1. Wire load models for synthesis

Wire load modeling allows us to estimate the effect of wire length and fanout on the resistance, capacitance, and area of nets. Synthesizer uses these physical values to calculate wire delays and circuit speeds. Semiconductor vendors develop wire load models, based on statistical information specific to the vendors’ process. The models include coefficients for area, capacitance, and resistance per unit length, and a fanout-to-length table for estimating net lengths (the number of fanouts determines a nominal length).

Wire load models

1.    Wire load models

Extraction data from already routed designs are used to build a lookup table known as the wire load model (WLM). WLM is based on the statistical estimates of R and C based on “Net Fan-out”.

Operating Condition: Operating Temperature Variation

8.3. Operating Temperature Variation

Temperature variation is unavoidable in the everyday operation of a design. Effects on performance caused by temperature fluctuations are most often handled as linear scaling effects, but some submicron silicon processes require nonlinear calculations.

Operating Condition: Supply Voltage Variation

8.2. Supply Voltage Variation

The design’s supply voltage can vary from the established ideal value during day-to-day operation. Often a complex calculation (using a shift in threshold voltages) is employed, but a simple linear scaling factor is also used for logic-level performance calculations.

Operating Condition: Process Variation

8.1. Process Variation

This variation accounts for deviations in the semiconductor fabrication process. Usually process variation is treated as a percentage variation in the performance calculation. Variations in the process parameters can be impurity concentration densities, oxide thicknesses and diffusion depths. These are caused bye non uniform conditions during depositions and/or during diffusions of the impurities. This introduces variations in the sheet resistance and transistor parameters such as threshold voltage. Variations are in the dimensions of the devices, mainly resulting from the limited resolution of the photolithographic process. This causes (W/L) variations in MOS transistors.

Operating conditions

1.     Operating conditions

Sources of variation in performance of a chip are due to:

Ø  Process variation (P)

Ø  Supply voltage (V)

Ø  Operating Temperature (T)

.lib: Cell description

7.2.4. Cell description

A cell description in the logic library contains variety of attributes describibing the function, timing, power and any other related information of the cell.

.lib: Wire Load Models

7.2.3.3. Wire Load Models

Wire load models contain informations that synthnesis tool utilizes to estimate interconnect wiring delays during logic synthesis phase of the design. Logic library includes several models approarpriate to different sizes of the design.

.lib: Operating Conditions:

7.2.3.2. Operating Conditions:

This section models the environmental variations of IC. These are known as Process, Voltage, and temperature variations. In short it is called PVT.

 

A set of values of PVT is known as operating condition. A logic library is characterised for one set of operating condition. Generally there are different libraries specific to different operating condition. There are three operating conditions very commonly used in ASIC synthesis and implementation. Based on the affect on cell delay due to the variation in PVT these classifications are made.

They are:

Ø  worst (also called ‘max’ or ‘slow’)à library in which cells are characterised for maximum delay

Ø  best(also called ‘min’ or ‘fast’)àlibrary in which cells are characterised for minimum delay

Ø  nominal(also called ‘typical’ or ‘normal’)àlibrary in which cells are characterised for typical delay

Eg.:

  /* Operation Conditions */

  nom_process                     : 1.00;

  nom_temperature                 : 125.00;

  nom_voltage                     : 0.95;

 

  voltage_map (VDD,0.95);

  voltage_map (VSS,0.00);

 

  define(process_corner, operating_conditions, string);

  operating_conditions (slow) {

    process_corner : "SlowSlow";

    process       : 1.00;

    voltage       : 0.95;

    temperature   : 125.00;

    tree_type     : balanced_tree;

  }

  default_operating_conditions : slow;

.lib: Environment Description

7.2.3. Environment Description

7.2.3.1. Scaling Factors:

The scaling factors (also called as K-factors) are multipliers that provide flexibility for derating the delay values based on PVT.  If PVT changes by a particular value then how to calculate parameter like cell delay or net delay? using these K-factors that can be accomplished.

.lib: Library level attributes

7.2.2. .lib: Library level attributes

Library level attributes section explains technolgy type, date, revision. It also gives units of volt, amps, time, capacitance etc which are used in the library.

 

Eg.:

  /* General Attributes */

  technology                        (cmos);

  delay_model                     : table_lookup;

  in_place_swap_mode              : match_footprint;

  library_features                  (report_delay_calculation,report_power_calculation);

 

  /* Units Attributes */

  time_unit                       : "1ns";

  leakage_power_unit              : "1nW";

  voltage_unit                    : "1V";

  current_unit                    : "1mA";

  pulling_resistance_unit         : "1kohm";

  capacitive_load_unit              (1,ff);

Logic Library

7.1 Logic Library

Logic synthesis relevant information are contained in logic libraries. Logic libraries does not contain any physical information of the logic gates. Logic library is a text file. Initially its development were done by a company called “liberty” which was later got acquired by EDA company Synopsys. Hence usual extension of logic libray is .lib and is known as liberty format logic library. This is now universally accepted and used by all fabrication houses and EDA companies.

 

Logic library has timing, area and power information pertaining to all logic gates. These characteristics include information such as cell names, pin names, delay arcs, and pin loading.

 

The technology library also defines the conditions such as the maximum transition time for nets, maximum capacitance and maximim fanout loading. These conditions are called design rule constraints.

 

In addition to cell information and design rule constraints, specify the operating conditions and wire load models specific to that technology are specified in technology library.

 

Net delay models in logic libraries are calculated from different models known as:

Ø  Nonlinear delay models (NLDMs)

Ø  Composite Current Source (CCS) models

 

7.2 Basics of Logic Library (.lib)

The contents of logic library can be broadly classified as below:

Ø  Library group

Ø  Library level attributes

Ø  Environment Description

Ø  Cell description

 

7.2.1. Library group

This gives part specifies general information such as library name regarding library.

Technology libraries :.lib

1.     Technology libraries :.lib

Technology library is a collection gates along with characteristics information of it. Technology libraries are provided by fabrication house (such as TSMC, UMC etc.) based on technology of manufacturing. Thus technology libraries contain information about the characteristics and functions of each logic cell provided in a semiconductor vendor’s library.  Technology libraries are distributed and maintained by semiconductor vendors (i.e. fabrication houses).

 

Thus a standard logic cell library consists of:

Ø  Logic cells of varied drive strength

Ø  Logic cells of varied number of inputs.

Ø  Inverters and buffers with equal rise and fall delay.

Ø  Complex cells such as AOI, OAI

Ø  Variety of both +ve and –ve edge triggered flip flops with different drive strengths,  set reset options

Ø  special cells: clock gating, Isolation, AOB etc.

Inputs and output from ASIC synthesis flow

6.2. Inputs and output from ASIC synthesis flow

Outcome of Synthesis is Gate level netlist which is again in Standard Verilog format. Netlists can be simulated as well which we call as Gate Level Simulation.

6.2.1. Register Transfer Level (RTL) Representation

RTL is the functional specification of the design to logic synthsis which is represented by HDLs.

Ø  Register: Storage element like F-F, latches

Ø  Transfer: Transfer data between input, output and register using combinational logic.

Ø  Level: Level of Abstraction modeled using HDL.

6.2.2. Constraints

The major objective of the logic synthesis is to meet the optimization constraints specified by the designer. Timing, area and power targets are the optimization constraints.

Ø  Timing Constraints: The synthesis tool tries to meet the setup and hold timing constraints on the sequential logic in the design.

Ø  Area constraints: Area constraints specifies maximum area for a design.

Ø  Power Constraints: Power constraints specifies the maximum power consumption for the design.

 

6.2.3. Target Library

 Target library is standard cell library corresponding to a particular technology node (eg. 45nm). This is a collection of combinational logic gates and sequential logic elements which are used to convert HDL to gate level netlist.

 

If logic synthesis is carried ou for FPGAs then HDL description is translated and mapped to LUTs, flip-flops and block RAMs.  For FPGA implementation separate synthesis tool is required. ASIC synthesis tool can’t synthesize the HDL into FPGA omplemtable netlist.

 

A clean technology independent HDL description of design can be synthesized to any technology node. This can also be targeted for FPGA implementations.

 

ASIC Synthesis: Synthesis definition, goals

1.     ASIC Synthesis

6.1. Synthesis definition, goals

Synthesis is the process of transforming your HDL design into a gate-level netlist, given all the specified constraints and optimization settings.

Logic synthesis is the process of translating and mapping RTL code written in HDL (such as Verilog or VHDL ) into technology specific gate  level representation.

 

There are 3 steps in Synthesis:

Ø  Translation: RTL code is translated to technolohgy independent representation. The converted logic is available in boolean equation form.

Ø  Optimization: Boolean equation is optimized using SoP or PoS optimization methods.

Ø  Technology mapping:  Technology independent boolean logic equations are mapped to technology dependant library logic gates based on design constraints, library of available technology gates.  This produces optimized gate level representation which is generally represented in Verilog.

 

 

Then the gate level circuit generated is logically optimized to meet the targets or goals set as per the user constraints. The clock frequency target is the number one goal that has to be met by the synthesis operation.

 

Avoid latch inference, Use Constants, General Coding guidelines for ASIC synthesis

5.2.15. Avoid latch inference

Ø  “if-else” statements must be end with ‘else’ statements. Else ‘unintentional latches’ will be realized (at output) due to the missing ‘else’ statement at the end.

Ø  Same is true for ‘case’ statement. ‘default’ statement must be added.

 

Work Around:

Either include all possible combination of inputs or initialise the value before the loop starts.

Eg.:

if(z)   a=b;

Above code will infer a latch. Because if z=1, value of ‘a’ is defined. But if z=0 value of ‘a’ is not specified. Hence it is assumed that  previous value has to be retained and hence latch is infered.

 

Eg.:

module latch_inf_test(a, x, y, t, out);

input [2:0] a;

input x, y, t;

output out; reg out;

 

always @(a or x or y or t)

begin

case(a)

                   3’b001:out=x;

                   3’b010:out=y;

                   3’b100:out=t;

endcase

end

endmodule

 

 

Eg.:

module case_latch(dout,sel,a,b,c);

input [1:0] sel;

input a,b,c;

output dout;

reg dout;

 

always @(a or b or c or sel)

begin

case (sel)

2'b00 : dout = a;

2'b01 : dout = b;

2'b10 : dout = c;

endcase

end

endmodule

Preventing a Latch by Assigning a Default Value

module case_default(dout,sel,a,b,c);

input [1:0] sel;

input a,b,c;

output dout;

reg dout;

 

always @(a or b or c or sel)

begin

case (sel)

2'b00 : dout = a;

2'b01 : dout = b;

2'b10 : dout = c;

default : dout = 1'b0;

endcase

end

endmodule

5.2.16. Use Constants

Use constants instead of hard coded numeric values.

Below coding style is not recommended:

wire [15:0] input_bus;

reg [15:0] output bus;

 

Recommended coding style:

‘define INPUT_BUS_WIDTH 16

‘define OUTPUT_BUS_WIDTH 16

wire [INPUT_BUS_WIDTH-1:0] input_bus;

reg [OUTPUT_BUS_WIDTH-1:0] output_bus;

 

Keep constants and parameters definitions in separate file with naming convention such as design_name.constants.v and design_name.parameters.v

 

 

5.2.17. General Coding guidelines for ASIC synthesis

Ø  “Inference” of the logic should be given higher priority compared to instantiation of the logic.

Ø  File name and module name should be same.

Ø  A file should have only one module.

Ø  Use lowercase letters for ports, variables and signal names.

Ø  Use uppercase for constants, user defined types.

References

[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005

[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009

[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009