DRC constraints exist
in library. DRC constraints can’t be relaxed. They can be chosen from library.
These constraints are imposed upon the design by requirements specified in the
target technology library. This presides over optimization constraints to
realize a functional design.
DRC
constraints are:
set_max_fanout
: This is the number of loads a pin or port can drive.
set_max_fanout value object_list
# Specifies the max fanout value for ports or on a design. If for a
design, it specifies the max fanout for all
# output pins in the design.
Examples:
set_max_fanout 16 [get_pins UDFT0/JTAG/ZN]
set_max_fanout 50 [current_design]
set_max_transition: This is the
longest time for a transition from logic level 0 to 1 or 1 to 0 for an entire
design. “set_max_transition” can also be set on a particular net. If library
has a max transition of 3 and if user specifies set_max_transition a value of
2.5 then synthesis tool tries to meet 2.5.
set_max_transition [-clock_path] [-data_path] [-rise] [-fall] value
object_list
# Specifies the max transition time on a port or on a design. If
for a design, it specifies the max transition #on all pins in a design.
Example:
set_max_transition
0.2 UCLKDIV0/QN
set_max_capacitance: This constraint specifies the
maximum output capacitance of a cell. The maximim capacitance of the output pin
of a driving cell should be greater than or equal to the sum of the capacitance
of the pins of driven cells and net capacitance.
# Specifies the max capacitance for ports or on a design. If for a
design, it specifies the max capacitance #for all pins in the design.
Examples:
set_max_capacitance 0.2 [current_design]
set_max_capacitance 1 [all_outputs]
“set_max_capacitance” is similar to “set_max_transition”. The
difference is “set_max_capacitance” provides an option to directly specify and
control the output capacitance which indirectly controls transition. Hence it
is enough you specify either of these constraints but not both.
set_min_capacitance value object_list
# Specifies a minimum capacitance value for a port or on
pins in design.
Example:
set_min_capacitance
0.05 UPHY0/UCNTR/B1
References
[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005
[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005
[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009
[BH] J. Bhasker,
Rakesh Chadha, Static Timing Analysis
for Nanometer Designs A Practical Approach, 2009
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