7.1 Logic Library
Logic synthesis relevant information are
contained in logic libraries. Logic libraries does not contain any physical
information of the logic gates. Logic library is a text file. Initially its
development were done by a company called “liberty” which was later got
acquired by EDA company Synopsys. Hence usual extension of logic libray is .lib
and is known as liberty format logic library. This is now universally accepted
and used by all fabrication houses and EDA companies.
Logic library has timing, area and power
information pertaining to all logic gates. These characteristics include information
such as cell names, pin names, delay arcs, and pin loading.
The technology library also defines the
conditions such as the maximum transition time for nets, maximum capacitance
and maximim fanout loading. These conditions are called design rule
constraints.
In addition to cell information and
design rule constraints, specify the operating conditions and wire load models
specific to that technology are specified in technology library.
Net delay models in logic libraries are
calculated from different models known as:
Ø Nonlinear
delay models (NLDMs)
Ø Composite
Current Source (CCS) models
7.2 Basics of
Logic Library (.lib)
The
contents of logic library can be broadly classified as below:
Ø Library
group
Ø
Library level attributes
Ø
Environment Description
Ø Cell
description
7.2.1. Library
group
This gives part specifies general
information such as library name regarding library.
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