Outcome of Synthesis is Gate level
netlist which is again in Standard Verilog format. Netlists can be simulated as
well which we call as Gate Level Simulation.
6.2.1.
Register Transfer Level (RTL) Representation
RTL is the functional specification of
the design to logic synthsis which is represented by HDLs.
Ø Register: Storage element
like F-F, latches
Ø Transfer: Transfer data between
input, output and register using combinational logic.
Ø Level: Level of
Abstraction modeled using HDL.
6.2.2.
Constraints
The major objective of the logic
synthesis is to meet the optimization constraints specified by the designer.
Timing, area and power targets are the optimization constraints.
Ø Timing Constraints: The
synthesis tool tries to meet the setup and hold timing constraints on the
sequential logic in the design.
Ø Area constraints: Area
constraints specifies maximum area for a design.
Ø Power Constraints: Power
constraints specifies the maximum power consumption for the design.
6.2.3.
Target Library
Target library is standard cell library
corresponding to a particular technology node (eg. 45nm). This is a collection
of combinational logic gates and sequential logic elements which are used to
convert HDL to gate level netlist.
If logic synthesis is carried ou for
FPGAs then HDL description is translated and mapped to LUTs, flip-flops and
block RAMs. For FPGA implementation
separate synthesis tool is required. ASIC synthesis tool can’t synthesize the
HDL into FPGA omplemtable netlist.
A
clean technology independent HDL description of design can be synthesized to
any technology node. This can also be targeted for FPGA implementations.
Thanks a lot for sharing the valuable information with an helpful content which is useful for the beginners. chip level training in Hyderabad
ReplyDelete