.lib: Wire Load Models

7.2.3.3. Wire Load Models

Wire load models contain informations that synthnesis tool utilizes to estimate interconnect wiring delays during logic synthesis phase of the design. Logic library includes several models approarpriate to different sizes of the design.

  /* Wire load tables */

 

  wire_load("1K_hvratio_1_4") {

    capacitance : 1.774000e-01;

    resistance : 3.571429e-03;

    slope : 5.000000;

    fanout_length( 1, 1.3207 );

    fanout_length( 2, 2.9813 );

    fanout_length( 3, 5.1135 );

    fanout_length( 4, 7.6639 );

    fanout_length( 5, 10.0334 );

    fanout_length( 6, 12.2296 );

    fanout_length( 8, 19.3185 );

  }

 

  wire_load("1K_hvratio_1_2") {

    capacitance : 1.774000e-01;

    resistance : 3.571429e-03;

    slope : 5.000000;

    fanout_length( 1, 1.3216 );

    fanout_length( 2, 2.8855 );

    fanout_length( 3, 4.6810 );

    fanout_length( 4, 6.7976 );

    fanout_length( 5, 9.4037 );

    fanout_length( 6, 13.0170 );

    fanout_length( 8, 24.1720 );

  }