Avoid latch inference, Use Constants, General Coding guidelines for ASIC synthesis

5.2.15. Avoid latch inference

Ø  “if-else” statements must be end with ‘else’ statements. Else ‘unintentional latches’ will be realized (at output) due to the missing ‘else’ statement at the end.

Ø  Same is true for ‘case’ statement. ‘default’ statement must be added.

 

Work Around:

Either include all possible combination of inputs or initialise the value before the loop starts.

Eg.:

if(z)   a=b;

Above code will infer a latch. Because if z=1, value of ‘a’ is defined. But if z=0 value of ‘a’ is not specified. Hence it is assumed that  previous value has to be retained and hence latch is infered.

 

Eg.:

module latch_inf_test(a, x, y, t, out);

input [2:0] a;

input x, y, t;

output out; reg out;

 

always @(a or x or y or t)

begin

case(a)

                   3’b001:out=x;

                   3’b010:out=y;

                   3’b100:out=t;

endcase

end

endmodule

 

 

Eg.:

module case_latch(dout,sel,a,b,c);

input [1:0] sel;

input a,b,c;

output dout;

reg dout;

 

always @(a or b or c or sel)

begin

case (sel)

2'b00 : dout = a;

2'b01 : dout = b;

2'b10 : dout = c;

endcase

end

endmodule

Preventing a Latch by Assigning a Default Value

module case_default(dout,sel,a,b,c);

input [1:0] sel;

input a,b,c;

output dout;

reg dout;

 

always @(a or b or c or sel)

begin

case (sel)

2'b00 : dout = a;

2'b01 : dout = b;

2'b10 : dout = c;

default : dout = 1'b0;

endcase

end

endmodule

5.2.16. Use Constants

Use constants instead of hard coded numeric values.

Below coding style is not recommended:

wire [15:0] input_bus;

reg [15:0] output bus;

 

Recommended coding style:

‘define INPUT_BUS_WIDTH 16

‘define OUTPUT_BUS_WIDTH 16

wire [INPUT_BUS_WIDTH-1:0] input_bus;

reg [OUTPUT_BUS_WIDTH-1:0] output_bus;

 

Keep constants and parameters definitions in separate file with naming convention such as design_name.constants.v and design_name.parameters.v

 

 

5.2.17. General Coding guidelines for ASIC synthesis

Ø  “Inference” of the logic should be given higher priority compared to instantiation of the logic.

Ø  File name and module name should be same.

Ø  A file should have only one module.

Ø  Use lowercase letters for ports, variables and signal names.

Ø  Use uppercase for constants, user defined types.

References

[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005

[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009

[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009