Reset logic guidelines, Registered outputs and Incomplete sensitivity list

5.2.12. Reset logic guidelines

Synchronous Reset:

Advantages:

Ø  Easy to synthesize, just another synchronous input to the design.

Disadvantages:

Ø  Require a free running clock. At power-up clock is must for reset.

Asynchronous Reset:

Advantages:

Ø  Doesn’t require a free running clock.

Ø  Uses separate input on flip flop, so it doesn’t affect flop data timing.

Disadvantages:

Ø  Harder to implement. Considered as high fanout net

Ø  STA, simulation, DFT becomes difficult

 

5.2.13. Registered outputs

All outputs should be registered and combinational logic should be either at the input section or in between two registered stages of a module.

 

5.2.14. Incomplete sensitivity list

Sensitive list should contain all inputs. If inputs are missed in the sensitivity list, then the changes of that inputs will not be recognized by simulator. Synthesized logic in most cases may correct for the blocks containing incomplete sensitivity list. But this may cause simulation mismatches between source RTL and synthesized netlist. Generally synthesis tools issue a warning for the “always” block having incomplete sensitivity list. Registers can also be added in the sensitive list.

References

[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005

[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009

[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009