Reset logic guidelines, Registered outputs and Incomplete sensitivity list

5.2.12. Reset logic guidelines

Synchronous Reset:

Advantages:

Ø  Easy to synthesize, just another synchronous input to the design.

Disadvantages:

Ø  Require a free running clock. At power-up clock is must for reset.

Asynchronous Reset:

Advantages:

Ø  Doesn’t require a free running clock.

Ø  Uses separate input on flip flop, so it doesn’t affect flop data timing.

Disadvantages:

Ø  Harder to implement. Considered as high fanout net

Ø  STA, simulation, DFT becomes difficult

 

5.2.13. Registered outputs

All outputs should be registered and combinational logic should be either at the input section or in between two registered stages of a module.

 

5.2.14. Incomplete sensitivity list

Sensitive list should contain all inputs. If inputs are missed in the sensitivity list, then the changes of that inputs will not be recognized by simulator. Synthesized logic in most cases may correct for the blocks containing incomplete sensitivity list. But this may cause simulation mismatches between source RTL and synthesized netlist. Generally synthesis tools issue a warning for the “always” block having incomplete sensitivity list. Registers can also be added in the sensitive list.

References

[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005

[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009

[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009

Clock logic guidelines

5.2.11. Clock logic guidelines

In case of multiple clocks in the design, make sure that clock generation and reset logics are written in one module for better handling in synthesis. If a clock is used in different modules of different heirarchy then keep clock names common across all the modules. This makes constraining that clock easier and also supports better handling of synthesis scripts.

 

Ø  Don’t use mixed clock edges

mixing of edge sensitive and level sensitive lists are not allowed. Below code is a wrong one.

always @(posedge clk or posedge rst)

 

Ø  Avoid clock buffers or any other logic

If any signal crosses multiple clock domains having different clock frequencies then those signals must be properly synchronised with synchronous logic. Synthesis tools can’t optimize any timing paths between asynchronous clock domains.

References

[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005

[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009

[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009

Technology independent RTL coding

5.2.9. Technology independent RTL coding

Write HDL code in technology independent fasion. This helps reusage of the HDL code for any technology node. Do not hard code logic gates from the technology library unless it is necessary to meet critical timing issues.

 

5.2.10. Pads separate from core logic

Pads are instantiated like any other module instantiation. If design has large number of I/O pads it is recommended to keep the pad instantiations in a separate file. Note that pads are technology dependant and hence the above recommendation!

References

[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005

[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009

[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009

RTL Coding for Logic Synthesis

1.1. Synthesizable and Non-Synthesizable Verilog constructs

	Synthesizable	Non-Synthesizable
Basic	Identifiers, escaped identifiers, Sized constants (b, o, d, h), Unsized constants (2'b11, 3'07, 32'd123, 8'hff), Signed constants (s) 3'bs101, module, endmodule, macromodule, ANSI-style module, task, and function port lists	system tasks, real constants
Data types	wire, wand, wor, tri, triand, trior, supply0, supply1, trireg (treated as wire), reg, integer, parameter, input, output, inout, memory(reg [7:0] x [3:0];), N-dimensional arrays,	real, time, event, tri0, tri1
Module instances	Connect port by name, order, Override parameter by order, Override parameter by name, Constants connected to ports, Unconnected ports, Expressions connected to ports,	Delay on built-in gates
Generate statements	if,case,for generate, concurrent begin end blocks, genvar,
Primitives	and, or, nand, nor, xor, xnor,not, notif0, notif1, buf, bufif0, bufif1, tran,	User defined primitives (UDPs), table, pullup, pulldown, pmos, nmos, cmos, rpmos, rnmos, rcmos, tranif0, tranif1, rtran, rtranif0, rtranif1,
Operators and expressions	+, - (binary and unary)
Bitwise operations	&, |, ^, ~^, ^~
Reduction operations	&, |, ^, ~&, ~|, ~^, ^~, !, &&, || , ==, !=, <, <=, >, >=, <<, >>, <<< >>>, {}, {n{}}, ?:, function call	===, !==
Event control	event or, @ (partial), event or using comma syntax, posedge, negedge (partial),	Event trigger (->), delay and wait (#)
Bit and part selects	Bit select, Bit select of array element, Constant part select, Variable part select ( +:, -:), Variable bit-select on left side of an assignment
Continuous assignments	net and wire declaration, assign	Using delay
Procedural blocks	always (exactly one @ required),	initial
Procedural statements	;, begin-end, if-else, repeat, case, casex, casez, default, for-while-forever-disable(partial),	fork, join
Procedural assignments	blocking (=), non-blocking (<=)	force, release
Functions and tasks	Functions, tasks
Compiler directives	`define, `undef, `resetall, `ifndef, `elsif, `line, `ifdef, `else, `endif, `include

Verilog HDL: Test Bench for 4 bit Counter

Test Bench for 4 bit Counter:

module tb_4bitcounter

reg tclk,trst;

wire [3:0]tq;

counter_4bit C1(.tq(q), .tclk(clk), .trst(rst)); instantiate counter to be tested.

initial

begin

#0 trst=1’b0; //tclk=1’b?;

#5 trst=1’b1; //tclk=1’b1;

#100 trst=1’b1; //tclk=1’b0;

end

Verilog HDL: Test Bench for 4-Bit Adder

Test Bench for 4-Bit Adder:

Verilog HDL: Test Bench

Test Bench

Using Verilog we can write a test bench to apply stimulus to the design and verify the results of the design. Up-front verification becomes very important as design size increases in size and complexity. This ensures simulation results matches with post synthesis results. A test bench can have two parts, the one generates input signals for the model to be tested while the other part checks the output signals from the design under test.

assign à assign values to registers, wires ; synthesizable and hence used in designs.

force , release: assign and deassign values to wire, reg within procedural block; used in verification

Verilog HDL: User-Defined Primitives(UDP)

User-Defined  Primitives(UDP) :

• One of the advanced concepts in verilog
• non synthesizable
• single output many iput
• consume very less memory
• I/Os must be scalar (i.e. bit)
• ‘z’ value is not supported.

primitive myprimitive(c,a,b)

input a,b;

output c;

table

0 0:0

0 1:0

1 0:0

1 1:0

endtable

endprimitive

 

Verilog HDL: Switch-level Modeling

Mos  switch  keywords :

->nmos(output,data,control)

->pmos(output,data,control)

->cmos(output,data,ncontrol,pcontrol);          

   

Verilog HDL: Timing and Delays In Verilog

Timing  and  Delays In Verilog:

Path  Delay  Modeling :-

Specify  Blocks :

->a  delay  between  a source  (input  or  inout)  pin  and  a  destination (output  or  inout)  pin   of  a  module  is  called  a   module path delay

->keywords for path delay : ‘specify’,’endspecify’

Eg :

module  m(out,a,b,c,d) ;

output  out;

input  a,b,c,d;

wire  e,f;

specify       //specify  block with path  delay  statements

         (a => out) = 9;  //for  full connection : (a,b*>out) = 9;

         (b=> out) = 9; 

         (c => out) = 11;  //for  full connection : (c,d*>out) = 11;

         (d => out) = 11; 

endspecify

and a1(e,a,b);

and a2(f,c,d);

and a3(out,e,f);

endmodule

Note :

Specify block  is  a  separate  block  in  the  module  and  does  not  appear  under  any  other  block, such  as  initial  or  always.

“specparam”  à  special  parameter  declaration  for  use inside  a specify  block ;  same  as  ‘parameter’   but  only  within  ‘specify’  block.

Rise, fall  and turn off delays :-

->if  only  one  delay  is  specified  , this  value  is  used  for  all  transitions.

->if  two  delays  specified, they  refer  to  the  rise  and fall delay values. The turn-off  delay

Is the minimum of  the  two delays.

->if  all  3  delays  are  specified, they refer  to rise, fall and turn-off delay values.

Eg :   and   #(5)  a1 (out,i1,i2);   //delay  of   5 for all transitions

          and   #(4,6)  a2 (out,i1,i2);  //rise=4,fall=6

          bufif0  #(3,4,5)  b1(out,in,control);   //rise=3,fall=4,turn-off=5

Min/Typ/Max   Values :

Eg1 :  and  #(4:5:6)   a1(out,i1,i2);

Here  4  is minimum  delay(+min delays)

5 is typical  delay(+ty  delays)

6  is  maximum delay(+max  delays)

Eg2 :

and   #(2:3:4,3:4:5,4:5:6)  a3(out,i1,i2);

           Here  2-rise,3-fall,4-turn off  min delays

           3-rise,4-fall,5-turn off  typdelays

            4-rise,5-fall,6-turn off  maxdelays

Timing  checks : $setup  and   $hold :

->$setup,  $hold,  $width

->all  timing  checks  must  be  inside  ‘specify’  blocks

$setup  task  :

$setup (data_event,reference_event,limit);

Data_event : signal that is monitored for violations

Reference_event :  signal that establishes  a  reference  for  monitoring  the  data_event  signal

Limit  :minimum  time  required  for  setup  of  data  event.

$hold   task :

$hold  (reference_event,data_event,limit);

$width  task :

$width (reference_event,limit);

Reference_event : Edge  triggered  event(edge  transition  of  a  signal)

Limit  :  minimum  width  of  the  pulse

Verilog HDL: System Tasks, File Related Operations, Compiler Directives

System  Tasks:

->all  system  tasks  appear  in  the  form  $

->operations   such  as  displaying  on  the  screen,  monitoring  values  of  nets,  stopping,  and  finishing  are  done  by  system tasks.

$display :  system  task  for  displaying  values  of  variables  or  strings   or   expressions very much   similar to  “printf”  in  C

Eg:  $display (p1,p2,p3,………pn);     where  p1,p2,p3  etc.  can  be  quoted  strings or variables or  expressions.