5.2.9. Technology
independent RTL coding
Write
HDL code in technology independent fasion. This helps reusage of the HDL code
for any technology node. Do not hard code logic gates from the technology
library unless it is necessary to meet critical timing issues.
5.2.10. Pads
separate from core logic
Pads
are instantiated like any other module instantiation. If design has large
number of I/O pads it is recommended to keep the pad instantiations in a
separate file. Note that pads are technology dependant and hence the above
recommendation!
References
[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005
[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005
[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009
[BH] J. Bhasker,
Rakesh Chadha, Static Timing Analysis
for Nanometer Designs A Practical Approach, 2009
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