Verilog HDL: Test Bench

Test Bench

Using Verilog we can write a test bench to apply stimulus to the design and verify the results of the design. Up-front verification becomes very important as design size increases in size and complexity. This ensures simulation results matches with post synthesis results. A test bench can have two parts, the one generates input signals for the model to be tested while the other part checks the output signals from the design under test.

assign à assign values to registers, wires ; synthesizable and hence used in designs.

force , release: assign and deassign values to wire, reg within procedural block; used in verification

Voltage Scaling and DVFS

Voltage Scaling

Reducing the power supply voltage is the effective technique to reduce dynamic power with the speed penalty. Keeping all others factors constant if power scaling is scaled down propagation delay will increase. This can be compensated by scaling down the threshold voltage to the same extent as the supply voltage. This allows the circuit to produce the same speed performance at a lower Vdd. At the same time smaller threshold voltages lead to smaller noise margin and increased leakage current.

Dynamic Voltage and Frequency Scaling (DVFS)

We know that supply voltage can be reduced if frequency of operation is reduced. If reduction in supply voltage is quadratic then approximately cubic reduction of power consumption can be achieved. However, it should be noted that frequency reduction slows the operation.

The above mentioned relation between energy and voltage is not always true. The authors in [1] showed that quadratic relationship between energy and Vdd deviates as Vdd is scaled down into the sub threshold voltage level. Sub threshold leakage current increases exponentially with the supply voltage. Since in sub threshold operation the on current takes the form of sub threshold current delay increases exponentially with voltage scaling. At very low voltages dynamic power reduces quadratically. But the leakage energy increases with supply voltage reduction since leakage energy is linear with the circuit delay. Hence dynamic and leakage power becomes comparable in sub threshold voltage region.

According to Bo Zhai et al. [1] dynamic voltage and frequency scaling is very popular low power technique. But larger voltage ranges does not improve power efficiency. They showed that for sub threshold supply voltages, leakage energy becomes dominant, making "just in time completion" energy inefficient. They also showed that extending voltage range below half Vdd will improve the energy efficiency for most processor designs while extending this range to sub threshold operations is beneficial only for specific applications. One of the important points to be noted from their study is DVFS in sub threshold voltage range is never energy efficient.

References

[1] Bo Zhai, David Blaauw, Dennis Sylvester and Krisztian Flaunter, "Theoretical and Practical Limits of Dynamic Voltage Scaling", DAC , San Diago, California, USA, pp.868-873, June 7-11, 2004