Power Planning

There are two types of power planning and management. They are core cell power management and I/O cell power management. In former one VDD and VSS power rings are formed around the core and macro. In addition to this straps and trunks are created for macros as per the power requirement. In the later one, power rings are formed for I/O cells and trunks are constructed between core power ring and power pads. Top to bottom approach is used for the power analysis of flatten design while bottom up approach is suitable for macros.

The power information can be obtained from the front end design. The synthesis tool reports static power information. Dynamic power can be calculated using Value Change Dump (VCD) or Switching Activity Interchange Format (SAIF) file in conjunction with RTL description and test bench. Exhaustive test coverage is required for efficient calculation of peak power. This methodology is depicted in Figure (1).

For the hierarchical design budgeting has to be carried out in front end. Power is calculated from each block of the design. Astro works on flattened netlist. Hence here top to bottom approach can be used. JupiterXT can work on hierarchical designs. Hence bottom up approach for power analysis can be used with JupiterXT. IR drops are not found in floor planning stage. In placement stage rails are get connected with power rings, straps, trunks. Now IR drops comes into picture and improper design of power can lead to large IR drops and core may not get sufficient power.

Figure (1) Power Planning methodology

Below are the calculations for flattened design of the SAMM. Only static power reported by the Synthesis tool (Design Compiler) is used instead of dynamic power.

• The number of the core power pad required for each side of the chip

= total core power / [number of side*core voltage*maximum allowable current for a I/O pad]

= 236.2068mW/ [4 * 1.08 V * 24mA] (Considering design SAMM)

= 2.278

~ 2

Therefore for each side of the chip 2 power pads (2 VDD and 2 VSS) are added.

• Total dynamic core current (mA)

= total dynamic core power / core voltage

= 236.2068mW / 1.08V

= 218.71 mA

• Core PG ring width

= (Total dynamic core current)/ (No. of sides * maximum current density of the metal layer used (Jmax) for PG ring)
=218.71 mA/(4*49.5 mA/µm)
~1.1 µm
~2 µm

• Pad to core trunk width (µm)

= total dynamic core current / number of sides * J_max where Jmax is the maximum current density of metal layer used

= 218.71 mA / [4 * 49.5 mA/µm]

= 1.104596 µm

Hence pad to trunk width is kept as 2µm.

Using below mentioned equations we can calculate vertical and horizontal strap width and required number of straps for each macro.

• Block current:

I_block= P_block / V_ddcore

• Current supply from each side of the block:

I_top=I_bottom= { I_block *[W_block / (W_block +H_block)] }/2

I_left=I_right= { I_block *[H_block / (W_block +H_block)] }/2

• Power strap width based on EM:

W_{strap_vertical} =I_top / J_metal

W_{strap_horizontal} =I_left / J_metal

• Power strap width based on IR:

W_{strap_vertical} >= [ I_top * R_oe * H_block ] / 0.1 * VDD

W_{strap_horizontal} >= [ I_left * R_oe * W_block ] / 0.1 * VDD

• Refresh width:

W_{refresh_vertical} =3 * routing pitch +minimum width of metal (M4)

W_{refresh_horizontal} =3 * routing pitch +minimum width of metal (M3)

• Refresh number

N_{refresh_vertical} = max (W_{strap_vertical} ) / W_{refresh_vertical}

N_{refresh_horizontal} = max (W_{strap_horizontal} ) / W_{refresh_horizontal}

• Refresh spacing

S_{refresh_vertical} = Wblock / N_{refresh_vertical}

S_{refresh_horizontal} = Hblock / N_{refresh_horizontal}

Figure (2) Showing core power ring, Straps and Trunks

Related Articles

• Physical Design Flow
• Libraries
• Inputs–outputs from physical design process
• Floor Planning
• Timing Analysis in Physical Design
• Placement
• Clock Tree Synthesis (CTS)
• Routing

Multi Voltage Designs: Power Planning Issues

Efficient power planning is one of the key concerns of modern SoC
designs. In multi voltage designs providing power to the different
power domains is challenging. Every power domain requires independent
local power supply and grid structure and some designs may even have a
separate power pad. Separate power pad is possible in flip-chip
designs and power pad can be taken out near from the power domain.
Other chips have to take out the power pads from the periphery which
can put limit to the number of power domains.

Local on chip voltage regulation is good idea to provide multiple
voltages to different circuits. Unfortunately most of the digital CMOS
technologies are not suitable for the implementation of either
switched mode of operation or linear voltage regulations.

Separate power rail structure is required for each power domain. These
additional power rails introduce different levels of IR drop putting
limit to the achievable power efficiency.

Related Articles

Multiple Voltage ASIC/SoC Designs: Classification

Multiple Voltage Design Challenges

Multiple Voltage Designs: Timing Issues

Multiple Voltage Design Challenges

Level Shifters

Signals crossing from one voltage domain to another voltage domain has
to be interfaced through the level shifter buffers which appropriately
shifts the signal levels. Design of suitable level shifter is a
challenging job.

Timing Analysis

Timing analysis of the given design becomes simpler with the single
voltage as it can be performed for single performance point based on
the characterized libraries. Tools can optimize the design for worst
case PVT (Process, Voltage, temperature) conditions.

This is not the case with multi voltage designs. Libraries should be
characterized for different voltage levels that are used in the
design. EDA tool has to optimize individual blocks or subsystems and
also multiple voltage domains. This analysis becomes complex for
larger ASIC/SoC.

Floorplanning and Power Planning

Multiple power domain demands multiple power grid structure and a
suitable power distribution among them. For a larger ASIC/SoC more
careful floorplanning and power planning is essential

The speed in which different power domains switch on or off also
important. A low voltage power domain may activate early compared to
the the high voltage domain. Multi voltage designs pose additional
board level complexities. Separate power supply may necessary to
provide different power levels.

Related Articles

Multiple Voltage ASIC/SoC Designs: Classification

Multiple Voltage Designs: Timing Issues

Multiple Voltage Designs: Power Planning Issues