20 October 2007

Power Planning

There are two types of power planning and management. They are core cell power management and I/O cell power management. In former one VDD and VSS power rings are formed around the core and macro. In addition to this straps and trunks are created for macros as per the power requirement. In the later one, power rings are formed for I/O cells and trunks are constructed between core power ring and power pads. Top to bottom approach is used for the power analysis of flatten design while bottom up approach is suitable for macros.

The power information can be obtained from the front end design. The synthesis tool reports static power information. Dynamic power can be calculated using Value Change Dump (VCD) or Switching Activity Interchange Format (SAIF) file in conjunction with RTL description and test bench. Exhaustive test coverage is required for efficient calculation of peak power. This methodology is depicted in Figure (1).


For the hierarchical design budgeting has to be carried out in front end. Power is calculated from each block of the design. Astro works on flattened netlist. Hence here top to bottom approach can be used. JupiterXT can work on hierarchical designs. Hence bottom up approach for power analysis can be used with JupiterXT. IR drops are not found in floor planning stage. In placement stage rails are get connected with power rings, straps, trunks. Now IR drops comes into picture and improper design of power can lead to large IR drops and core may not get sufficient power.



Figure (1) Power Planning methodology

Below are the calculations for flattened design of the SAMM. Only static power reported by the Synthesis tool (Design Compiler) is used instead of dynamic power.

  • The number of the core power pad required for each side of the chip

= total core power / [number of side*core voltage*maximum allowable current for a I/O pad]

= 236.2068mW/ [4 * 1.08 V * 24mA] (Considering design SAMM)

= 2.278

~ 2

Therefore for each side of the chip 2 power pads (2 VDD and 2 VSS) are added.

  • Total dynamic core current (mA)

= total dynamic core power / core voltage

= 236.2068mW / 1.08V

= 218.71 mA

  • Core PG ring width
= (Total dynamic core current)/ (No. of sides * maximum current density of the metal layer used (Jmax) for PG ring)
=218.71 mA/(4*49.5 mA/µm)
~1.1 µm
~2 µm
  • Pad to core trunk width (µm)

= total dynamic core current / number of sides * Jmax where Jmax is the maximum current density of metal layer used

= 218.71 mA / [4 * 49.5 mA/µm]

= 1.104596 µm

Hence pad to trunk width is kept as 2µm.


Using below mentioned equations we can calculate vertical and horizontal strap width and required number of straps for each macro.

  • Block current:

Iblock= Pblock / Vddcore


  • Current supply from each side of the block:

Itop=Ibottom= { Iblock *[Wblock / (Wblock +Hblock)] }/2

Ileft=Iright= { Iblock *[Hblock / (Wblock +Hblock)] }/2


  • Power strap width based on EM:

Wstrap_vertical =Itop / Jmetal

Wstrap_horizontal =Ileft / Jmetal


  • Power strap width based on IR:

Wstrap_vertical >= [ Itop * Roe * Hblock ] / 0.1 * VDD

Wstrap_horizontal >= [ Ileft * Roe * Wblock ] / 0.1 * VDD


  • Refresh width:

Wrefresh_vertical =3 * routing pitch +minimum width of metal (M4)

Wrefresh_horizontal =3 * routing pitch +minimum width of metal (M3)


  • Refresh number

Nrefresh_vertical = max (Wstrap_vertical ) / Wrefresh_vertical

Nrefresh_horizontal = max (Wstrap_horizontal ) / Wrefresh_horizontal


  • Refresh spacing

Srefresh_vertical = Wblock / Nrefresh_vertical

Srefresh_horizontal = Hblock / Nrefresh_horizontal





Figure (2) Showing core power ring, Straps and Trunks

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12 comments:

  1. What about PG ring width?

    ReplyDelete
  2. core PG ring width= (total core current)/ (No. of sides * maximum current density of the metal layer used for PG ring)

    ReplyDelete
  3. I think that formulas for Current supply from each side of the block: should be

    Itop=Ibottom= { Iblock *[Wblock / (Wblock +Hblock)] }/2

    Ileft=Iright= { Iblock *[Hblock / (Wblock +Hblock)] }/2

    Could you please recheck?

    ReplyDelete
  4. I think that formulas for Current supply from each side of the block: should be

    Itop=Ibottom= { Iblock *[Wblock / (Wblock +Hblock)] }/2

    Ileft=Iright= { Iblock *[Hblock / (Wblock +Hblock)] }/2

    Could you please recheck?

    ReplyDelete
  5. What is Roe & routing pitch and from where we get these values???

    ReplyDelete
    Replies
    1. Hi, Roe is the sheet resistance of the metal layer used for the routing, that is,the resistivity rho divided by the thickness of the routing layer

      Delete
  6. how to draw PG mesh accurately?

    ReplyDelete
  7. where we get core voltage? its get from .lib library or not

    ReplyDelete
  8. Can any one tell.,
    steps to calculate powerplanning with formulaes in Vlsi chip design.

    ReplyDelete
  9. fro where we get maximum current density of metal value?

    ReplyDelete
  10. why it is using dynamic power to calculate pg, not static + dynamic? thank you.

    ReplyDelete

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