Physical Design Flow

The physical design flow is generally explained in the Figure (1.). In each section of the flow EDA tools available from the two main EDA companies-Synopsys and Cadence is also listed. In each and every step of the flow timing and power analysis can be carried out. If timing and power requirements are not met then either the whole flow has to be re-exercised or going back one or two steps and optimizing the design or incremental optimization may meet the requirements

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  1. what is the difference between the block level and full chip floorplanning...tell in detail

  2. what is the asic flow of the different vendors(synopsys,magma) can u post clearly and wer can i get the answer to this pls intimate si


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