Floor Planning

Floor plan determines the size of the design cell (or die), creates the boundary and core area, and creates wire tracks for placement of standard cells. [1]. It is also a process of positioning blocks or macros on the die.


Floor planning control parameters like aspect ratio, core utilization are defined as follows:

Aspect Ratio= Horizontal Routing Resources / Vertical Routing Resources

Core Utilization= Standard Cell Area / (Row Area + Channel Area)

Total 4 metal layers are available for routing in used version of Astro. M0 and M3 are horizontal and M2 and M4 are vertical layers. Hence aspect ratio for SAMM is 1. Total number of cells =1645; total number of nets=1837 and number of ports (excluding 16 power pads) = 60. The figure depicting floor plan-die size (µm) of SAMM is shown beside.

Top Design Format (TDF) files provide Astro with special instructions for planning, placing, and routing the design. TDF files generally include pin and port information. Astro particularly uses the I/O definitions from the TDF file in the starting phase of the design flow. [1]. Corner cells are simply dummy cells which have ground and power layers. The TDF file used for SAMM is given below. The SAMM IC has total 80 I/O pads out of which 4 are dummy pads. Each side of the chip has 20 pads including 2 sets of power pads. Number of power pads required for SAMM is calculated in power planning section. Design is pad limited (pad area is more than cell area) and inline bonding (same I/O pad height) is used.

define _cell (geGetEditCell)

;create power pads

;Core power supply instantiation for left side

dbCreateCellInst (geGetEditCell) "" "pv0i.FRAM" "vss1left" "0" "NO" '(0.0 0.0) "sam3"

dbCreateCellInst (geGetEditCell) "" "pvdi.FRAM" "vdd1left" "0" "NO" '(0.0 0.0) "sam3"

dbCreateCellInst (geGetEditCell) "" "pv0i.FRAM" "vss2left" "0" "NO" '(0.0 0.0) "sam3"

dbCreateCellInst (geGetEditCell) "" "pvdi.FRAM" "vdd2left" "0" "NO" '(0.0 0.0) "sam3"

;Core power supply instantiation for top side

dbCreateCellInst (geGetEditCell) "" "pv0i.FRAM" "vss1top" "0" "NO" '(0.0 0.0) "sam3"

dbCreateCellInst (geGetEditCell) "" "pvdi.FRAM" "vdd1top" "0" "NO" '(0.0 0.0) "sam3"

dbCreateCellInst (geGetEditCell) "" "pv0i.FRAM" "vss2top" "0" "NO" '(0.0 0.0) "sam3"

dbCreateCellInst (geGetEditCell) "" "pvdi.FRAM" "vdd2top" "0" "NO" '(0.0 0.0) "sam3"

;Core power supply instantiation for right side

dbCreateCellInst (geGetEditCell) "" "pv0i.FRAM" "vss1right" "0" "NO" '(0.0 0.0) "sam3"

dbCreateCellInst (geGetEditCell) "" "pvdi.FRAM" "vdd1right" "0" "NO" '(0.0 0.0) "sam3"

dbCreateCellInst (geGetEditCell) "" "pv0i.FRAM" "vss2right" "0" "NO" '(0.0 0.0) "sam3"

dbCreateCellInst (geGetEditCell) "" "pvdi.FRAM" "vdd2right" "0" "NO" '(0.0 0.0) "sam3"

;Core power supply instantiation for bottom side

dbCreateCellInst (geGetEditCell) "" "pv0i.FRAM" "vss1bottom" "0" "NO" '(0.0 0.0) "sam3"

dbCreateCellInst (geGetEditCell) "" "pvdi.FRAM" "vdd1bottom" "0" "NO" '(0.0 0.0) "sam3"

dbCreateCellInst (geGetEditCell) "" "pv0i.FRAM" "vss2bottom" "0" "NO" '(0.0 0.0) "sam3"

dbCreateCellInst (geGetEditCell) "" "pvdi.FRAM" "vdd2bottom" "0" "NO" '(0.0 0.0) "sam3"

;dummy cell instantiation

dbCreateCellInst (geGetEditCell) "" "pc3t02.FRAM" "dummy1" "0" "NO" '(0.0 0.0) "sam3"

dbCreateCellInst (geGetEditCell) "" "pc3t02.FRAM" "dummy2" "0" "NO" '(0.0 0.0) "sam3"

dbCreateCellInst (geGetEditCell) "" "pc3t02.FRAM" "dummy3" "0" "NO" '(0.0 0.0) "sam3"

dbCreateCellInst (geGetEditCell) "" "pc3t02.FRAM" "dummy4" "0" "NO" '(0.0 0.0) "sam3"

dbCreateCellInst (geGetEditCell) "" "pc3t02.FRAM" "dummy5" "0" "NO" '(0.0 0.0) "sam3"

;corner cell instantiation

dbCreateCellInst (geGetEditCell) "" "pfrelr.FRAM" "cornerll" "270" "NO" '(10 10) "sam3"

dbCreateCellInst (geGetEditCell) "" "pfrelr.FRAM" "cornerlr" "0" "NO" '(10 10) "sam3"

dbCreateCellInst (geGetEditCell) "" "pfrelr.FRAM" "cornerul" "180" "NO" '(10 10) "sam3"

dbCreateCellInst (geGetEditCell) "" "pfrelr.FRAM" "cornerur" "90" "NO" '(10 10) "sam3"

tdfPurgePadConstr

;==================================

;pad placement for corner cells

;==================================

pad "cornerll" "bottom"

pad "cornerur" "top"

pad "cornerlr" "right"

pad "cornerul" "left"

;==================================

;pad(I/O) placement for left side

;==================================

pad "U1065" "left" 1 ;a_row0[0]

pad "U1064" "left" 2 ;a_row0[1]

pad "U1063" "left" 3 ;a_row0[2]

pad "U1062" "left" 4 ;a_row0[3]

pad "U1069" "left" 5 ;a_row1[0]

pad "U1068" "left" 6 ;a_row1[1]

pad "U1067" "left" 7 ;a_row1[2]

pad "vdd1left" "left" 8

pad "vss1left" "left" 9

pad "vdd2left" "left" 10

pad "vss2left" "left" 11

pad "U1066" "left" 12 ;a_row1[3]

pad "U1073" "left" 13 ;a_row2[0]

pad "U1072" "left" 14 ;a_row2[1]

pad "U1071" "left" 15 ;a_row2[2]

pad "U1070" "left" 16 ;a_row2[3]

pad "U1118" "left" 17 ;clock

pad "U1116" "left" 18 ;chip enable

pad "dummy1" "left" 19

pad "dummy2" "left" 20

;==================================

;pad(I/O) placement for top side

;==================================

pad "U1077" "top" 1 ;b_col0[0]

pad "U1076" "top" 2 ;b_col0[1]

pad "U1075" "top" 3 ;b_col0[2]

pad "U1074" "top" 4 ;b_col0[3]

pad "U1081" "top" 5 ;b_col1[0]

pad "U1080" "top" 6 ;b_col1[1]

pad "U1079" "top" 7 ;b_col1[2]

pad "vdd1top" "top" 8

pad "vss1top" "top" 9

pad "vdd2top" "top" 10

pad "vss2top" "top" 11

pad "U1078" "top" 12 ;b_col1[3]

pad "U1085" "top" 13 ;b_col2[0]

pad "U1084" "top" 14 ;b_col2[1]

pad "U1083" "top" 15 ;b_col2[2]

pad "U1082" "top" 16 ;b_col2[3]

pad "U1117" "top" 17 ;reset

pad "U1119" "top" 18 ;mult_over

pad "dummy3" "top" 19

pad "dummy4" "top" 20

;==================================

;pad(I/O) placement for right side

;==================================

pad "U1100" "right" 1 ;c_row1[5]

pad "U1101" "right" 2 ;c_row1[4]

pad "U1102" "right" 3 ;c_row1[3]

pad "U1103" "right" 4 ;c_row1[2]

pad "U1104" "right" 5 ;c_row1[1]

pad "U1105" "right" 6 ;c_row1[0]

pad "U1086" "right" 7 ;c_row0[9]

pad "vdd1right" "right" 8

pad "vss1right" "right" 9

pad "vdd2right" "right" 10

pad "vss2right" "right" 11

pad "U1087" "right" 12 ;c_row0[8]

pad "U1088" "right" 13 ;c_row0[7]

pad "U1089" "right" 14 ;c_row0[6]

pad "U1090" "right" 15 ;c_row0[5]

pad "U1091" "right" 16 ;c_row0[4]

pad "U1092" "right" 17 ;c_row0[3]

pad "U1093" "right" 18 ;c_row0[2]

pad "U1094" "right" 19 ;c_row0[1]

pad "U1095" "right" 20 ;c_row0[0]

;==================================

;pad(I/O) placement for bottom side

;==================================

pad "dummy5" "bottom" 1

pad "U1121" "bottom" 2 ;test_se

pad "U1106" "bottom" 3 ;c_row2[9]

pad "U1107" "bottom" 4 ;c_row2[8]

pad "U1108" "bottom" 5 ;c_row2[7]

pad "U1109" "bottom" 6 ;c_row2[6]

pad "U1110" "bottom" 7 ;c_row2[5]

pad "vdd1bottom" "bottom" 8;

pad "vss1bottom" "bottom" 9

pad "vdd2bottom" "bottom" 10

pad "vss2bottom" "bottom" 11

pad "U1111" "bottom" 12 ;c_row2[4]

pad "U1112" "bottom" 13 ;c_row2[3]

pad "U1113" "bottom" 14 ;c_row2[2]

pad "U1114" "bottom" 15 ;c_row2[1]

pad "U1115" "bottom" 16 ;c_row2[0]

pad "U1096" "bottom" 17 ;c_row1[9]

pad "U1097" "bottom" 18 ;c_row1[8]

pad "U1098" "bottom" 19 ;c_row1[7]

pad "U1099" "bottom" 20 ;c_row1[6]

;=======================================

If TDF is free from syntax errors and pins are properly numbered in consecutive steps then TDF will be read successfully and message will be displayed on scheme window.

Aspect ratio of 0.65 is set which means 65% of the core area is used for cells and remaining 35% is for routing. Since channel less row arrangement is desired for area optimization row to core ratio can be kept at 1. Rows should be arranged horizontal, they are flipped and abutted and thus double back arrangement should be enabled.



Floor planned cell

Floor planned cell is shown above and its related die size is shown first itself. All dimensions are in µm. The total die size is approximately 1.9sqmm.


Reference

[1] Astro User Guide,Version X-2005.09, September 2005


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1 comment:

  1. Hello,
    You refer to two aspect ratios in this article. First one equated to the routing resources and the second one at the end for area. Can you kindly please explain the difference.


    Thank you,

    ReplyDelete

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