tag:blogger.com,1999:blog-2516717450266481889.post5401083308065520578..comments2024-03-22T12:53:39.867+05:30Comments on ASIC-System on Chip-VLSI Design: Power PlanningMuralihttp://www.blogger.com/profile/05927561262168582763noreply@blogger.comBlogger16125tag:blogger.com,1999:blog-2516717450266481889.post-21325222319970614422023-10-30T21:01:55.195+05:302023-10-30T21:01:55.195+05:30For power strap based on IR, why is "0.1"...For power strap based on IR, why is "0.1" being multiplied with VDD?S.C. Ramyahttps://www.blogger.com/profile/11552425615918471550noreply@blogger.comtag:blogger.com,1999:blog-2516717450266481889.post-53108969640757896202017-12-08T21:05:25.429+05:302017-12-08T21:05:25.429+05:30Its Physical Design point of view, push down means...Its Physical Design point of view, push down means in hierarchal top and block implementation , initial we design power mesh on top including blocks then we push the power mesh to blocks so construction by method block level power mesh physically align with top level power mesh Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2516717450266481889.post-67577738596170686702017-10-16T08:56:21.810+05:302017-10-16T08:56:21.810+05:30some people say our power planning was a push down...some people say our power planning was a push down structure, what does this mean?Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2516717450266481889.post-29081288786121375822017-07-02T18:10:47.880+05:302017-07-02T18:10:47.880+05:30dynamic power is the maximum consumed in the chip....dynamic power is the maximum consumed in the chip.Anonymoushttps://www.blogger.com/profile/11894258864368983483noreply@blogger.comtag:blogger.com,1999:blog-2516717450266481889.post-34255380623598547142017-03-01T08:55:33.399+05:302017-03-01T08:55:33.399+05:30why it is using dynamic power to calculate pg, not...why it is using dynamic power to calculate pg, not static + dynamic? thank you.Unknownhttps://www.blogger.com/profile/07619168245893235644noreply@blogger.comtag:blogger.com,1999:blog-2516717450266481889.post-25916253314135334822014-02-11T14:56:57.129+05:302014-02-11T14:56:57.129+05:30fro where we get maximum current density of metal ...fro where we get maximum current density of metal value?pruthvihttps://www.blogger.com/profile/06926829484415196170noreply@blogger.comtag:blogger.com,1999:blog-2516717450266481889.post-51752230382073187932012-10-30T20:51:36.119+05:302012-10-30T20:51:36.119+05:30Hi, Roe is the sheet resistance of the metal layer...Hi, Roe is the sheet resistance of the metal layer used for the routing, that is,the resistivity rho divided by the thickness of the routing layerAnonymousnoreply@blogger.comtag:blogger.com,1999:blog-2516717450266481889.post-2898662281700512942010-10-09T11:18:23.456+05:302010-10-09T11:18:23.456+05:30Can any one tell.,
steps to calculate powerplannin...Can any one tell.,<br />steps to calculate powerplanning with formulaes in Vlsi chip design.Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2516717450266481889.post-22147248052228557702010-07-22T11:45:12.693+05:302010-07-22T11:45:12.693+05:30where we get core voltage? its get from .lib libra...where we get core voltage? its get from .lib library or notravikumar chandrasekaranhttps://www.blogger.com/profile/10109838167086418515noreply@blogger.comtag:blogger.com,1999:blog-2516717450266481889.post-28184292098066538622009-06-24T15:04:19.945+05:302009-06-24T15:04:19.945+05:30how to draw PG mesh accurately?how to draw PG mesh accurately?Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2516717450266481889.post-40801746335621068312009-04-11T15:54:00.000+05:302009-04-11T15:54:00.000+05:30What is Roe & routing pitch and from where we ...What is Roe & routing pitch and from where we get these values???Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2516717450266481889.post-35146291743373503912008-12-24T22:02:00.000+05:302008-12-24T22:02:00.000+05:30what is Roe herewhat is Roe hereAnonymousnoreply@blogger.comtag:blogger.com,1999:blog-2516717450266481889.post-27810575175860066432008-03-26T01:41:00.000+05:302008-03-26T01:41:00.000+05:30I think that formulas for Current supply from each...I think that formulas for Current supply from each side of the block: should be<BR/><BR/>Itop=Ibottom= { Iblock *[Wblock / (Wblock +Hblock)] }/2 <BR/><BR/>Ileft=Iright= { Iblock *[Hblock / (Wblock +Hblock)] }/2<BR/><BR/>Could you please recheck?Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2516717450266481889.post-20153785553398605482008-03-26T01:38:00.000+05:302008-03-26T01:38:00.000+05:30I think that formulas for Current supply from each...I think that formulas for Current supply from each side of the block: should be<BR/><BR/>Itop=Ibottom= { Iblock *[Wblock / (Wblock +Hblock)] }/2 <BR/><BR/>Ileft=Iright= { Iblock *[Hblock / (Wblock +Hblock)] }/2<BR/><BR/>Could you please recheck?Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2516717450266481889.post-59226028113481035522008-03-24T13:54:00.000+05:302008-03-24T13:54:00.000+05:30core PG ring width= (total core current)/ (No. of ...core PG ring width= (total core current)/ (No. of sides * maximum current density of the metal layer used for PG ring)Muralihttps://www.blogger.com/profile/05927561262168582763noreply@blogger.comtag:blogger.com,1999:blog-2516717450266481889.post-19750311073889043192008-03-24T01:48:00.000+05:302008-03-24T01:48:00.000+05:30What about PG ring width?What about PG ring width?Anonymousnoreply@blogger.com