26 September 2007

Multi Voltage Designs: Timing Issues

Clock

Clock Tree Synthesis (CTS) tools should be aware of different power
domains and understand the level shifters to insert them in
appropriate places. Clock tree is routed through level shifters to
reach different power domains. Simultaneous timing analysis and
optimization is necessary for multiple voltage domains. Thus CTS
becomes more complex in multi voltage designs.

Static Timing Analysis (STA)


Timing analysis for single voltage design is easy.When it comes to
static voltage scaling it becomes little tougher job as analysis has
to be carried out for different voltages.This methodology requires
libraries which are characterized for different voltages used.


Multi level and dynamic voltage scaling pose a greater challenge. For
each supply voltage level or operating point constraints are
specified. There can be different operating modes for different
voltages. Constraints need not be same for all modes and voltages. The
performance target for each mode can vary. EDA tool should be capable
of handling all these situations simultaneously to carry out timing
analysis. Different constraints at different modes and voltages have
to be satisfied.


Related Articles

Multiple Voltage ASIC/SoC Designs: Classification

Multiple Voltage Design Challenges

Multiple Voltage Designs: Power Planning Issues



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