Signals crossing from one voltage domain to another voltage domain has
to be interfaced through the level shifter buffers which appropriately
shifts the signal levels. Design of suitable level shifter is a
challenging job.
Timing Analysis
Timing analysis of the given design becomes simpler with the single
voltage as it can be performed for single performance point based on
the characterized libraries. Tools can optimize the design for worst
case PVT (Process, Voltage, temperature) conditions.
This is not the case with multi voltage designs. Libraries should be
characterized for different voltage levels that are used in the
design. EDA tool has to optimize individual blocks or subsystems and
also multiple voltage domains. This analysis becomes complex for
larger ASIC/SoC.
Floorplanning and Power Planning
Multiple power domain demands multiple power grid structure and a
suitable power distribution among them. For a larger ASIC/SoC more
careful floorplanning and power planning is essential
The speed in which different power domains switch on or off also
important. A low voltage power domain may activate early compared to
the the high voltage domain. Multi voltage designs pose additional
board level complexities. Separate power supply may necessary to
provide different power levels.
Related Articles
Multiple Voltage ASIC/SoC Designs: Classification
Multiple Voltage Designs: Timing Issues
Multiple Voltage Designs: Power Planning Issues
This is padma doing project on physical design.
ReplyDeletei want to know how to calculate die area based on total area which we get from dc compiler.can u give details.
Total cell area is obtained from the area report from DC. Take squareroot of this. Obtained value is the approaximate height and width of the core area.
ReplyDeleteTotal area report provides the area considering pads also. Hence you can estimate what is tha extra area required for the pad.
Thus you can estimate die size. Remember that this is just an estimate. Actual die size can vary.
rgds
murali