26 September 2007

Multi Voltage Designs: Power Planning Issues

Efficient power planning is one of the key concerns of modern SoC
designs. In multi voltage designs providing power to the different
power domains is challenging. Every power domain requires independent
local power supply and grid structure and some designs may even have a
separate power pad. Separate power pad is possible in flip-chip
designs and power pad can be taken out near from the power domain.
Other chips have to take out the power pads from the periphery which
can put limit to the number of power domains.

Local on chip voltage regulation is good idea to provide multiple
voltages to different circuits. Unfortunately most of the digital CMOS
technologies are not suitable for the implementation of either
switched mode of operation or linear voltage regulations.

Separate power rail structure is required for each power domain. These
additional power rails introduce different levels of IR drop putting
limit to the achievable power efficiency.

Related Articles

Multiple Voltage ASIC/SoC Designs: Classification

Multiple Voltage Design Challenges

Multiple Voltage Designs: Timing Issues

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