.lib: Library level attributes

7.2.2. .lib: Library level attributes

Library level attributes section explains technolgy type, date, revision. It also gives units of volt, amps, time, capacitance etc which are used in the library.

 

Eg.:

  /* General Attributes */

  technology                        (cmos);

  delay_model                     : table_lookup;

  in_place_swap_mode              : match_footprint;

  library_features                  (report_delay_calculation,report_power_calculation);

 

  /* Units Attributes */

  time_unit                       : "1ns";

  leakage_power_unit              : "1nW";

  voltage_unit                    : "1V";

  current_unit                    : "1mA";

  pulling_resistance_unit         : "1kohm";

  capacitive_load_unit              (1,ff);

Logic Library

7.1 Logic Library

Logic synthesis relevant information are contained in logic libraries. Logic libraries does not contain any physical information of the logic gates. Logic library is a text file. Initially its development were done by a company called “liberty” which was later got acquired by EDA company Synopsys. Hence usual extension of logic libray is .lib and is known as liberty format logic library. This is now universally accepted and used by all fabrication houses and EDA companies.

 

Logic library has timing, area and power information pertaining to all logic gates. These characteristics include information such as cell names, pin names, delay arcs, and pin loading.

 

The technology library also defines the conditions such as the maximum transition time for nets, maximum capacitance and maximim fanout loading. These conditions are called design rule constraints.

 

In addition to cell information and design rule constraints, specify the operating conditions and wire load models specific to that technology are specified in technology library.

 

Net delay models in logic libraries are calculated from different models known as:

Ø  Nonlinear delay models (NLDMs)

Ø  Composite Current Source (CCS) models

 

7.2 Basics of Logic Library (.lib)

The contents of logic library can be broadly classified as below:

Ø  Library group

Ø  Library level attributes

Ø  Environment Description

Ø  Cell description

 

7.2.1. Library group

This gives part specifies general information such as library name regarding library.

Technology libraries :.lib

1.     Technology libraries :.lib

Technology library is a collection gates along with characteristics information of it. Technology libraries are provided by fabrication house (such as TSMC, UMC etc.) based on technology of manufacturing. Thus technology libraries contain information about the characteristics and functions of each logic cell provided in a semiconductor vendor’s library.  Technology libraries are distributed and maintained by semiconductor vendors (i.e. fabrication houses).

 

Thus a standard logic cell library consists of:

Ø  Logic cells of varied drive strength

Ø  Logic cells of varied number of inputs.

Ø  Inverters and buffers with equal rise and fall delay.

Ø  Complex cells such as AOI, OAI

Ø  Variety of both +ve and –ve edge triggered flip flops with different drive strengths,  set reset options

Ø  special cells: clock gating, Isolation, AOB etc.

Libraries In Physical Design

Technology libraries are integral part of the ASIC backend EDA tools. Important two libraries are briefly explained below.

Technology File Libraries

Technology file defines basic characteristic of cell library pertaining to a particular technology node. They are units used in the design, graphical characteristics like colors, stipple patterns, line styles, physical parameters of metal layers, coupling capacitances, capacitance models, dielectric values, device characteristics, design rules. These specifications are divided into technology file sections.

Units for power, voltage, current etc are defined in technology section.

The color section defines primary and display colors that a tool uses to display designs in the library.

Stipple pattern are defined in stipple sections.

Different layer definitions like its current density, width etc are defined in layer section.

Fringe capacitances generated by crossing of interconnects are defined in fringe cap section.

Similarly several other specifications like metal density, design rules that apply to design in library, place and route (P&R) rules, slot rule, resistance model are defined in their respective sections.

Standard Cell Libraries, I/O Cell Libraries, Special Cell Libraries

A standard cell library is a collection of pre designed layout of basic logic gates like inverters, buffers, ANDs, ORs, NANDs etc.

All the cells in the library have same standard height and have varied width. These standard cell libraries are known as reference libraries in Astro.

These reference libraries are technology specific and are generally provided by ASIC vendor like TSMC, Artisan, IBM etc. Standard cell height for 130 TSMC process is 3.65 µM.

In addition to standard cell libraries, reference libraries contain I/O and Power/Ground pad cell libraries. It also contain IP libraries for reusable IP like RAMs, ROMs and other pre-designed, standard, complex blocks.

The TSMC universal I/O libraries include several power/ground cells that supply different voltages to the core, pre-drivers and post drivers. Internal pull-up or pull-down is provided to some cells in I/O libraries.

Reference

[1] Astro User Guide, Version X-2005.09, September 2005

Related Articles

• Physical Design Flow
• Inputs–outputs from physical design process
• Floor Planning
• Power Planning
• Timing Analysis in Physical Design
• Placement
• Clock Tree Synthesis (CTS)
• Routing

Multiple Threshold (Multi Vt) Cell Libraries

With the technologies shrinking to 90nm, 30nm and below one of the
common ways to reduce leakage power is to use multiple Vt libraries.
Subthreshold leakage varies exponentially with the Vt comparated to
the weaker dependance of delay over Vt.

Libraries are offered in different versions each consisting of
standard Vt cells, low Vt cells and high Vt cells independant of each
other. Power and timing is optimized based on these libraries and they
offer good flexibility and opportunity to logic and physical synthesis
tool for optimization process.

Dual Vt synthesis flow has become quite common in 130nm and below
tehnology nodes. In this flow initial synthesis is carried out
targeting primary library which may be a low Vt or high Vt or normal
Vt library, and the second iteraton of synthesis and optimization is
performed based on secondary libraries which are also libraries
consistitng of multiple threshold cells.

Which library has to be used as primary library ?

This depends on the optimization target as per the design requirement.
In general, if optimization target is power performance, first
syntheize the design using the high Vt cell library which achieves
lowest leakage power. In the next iteration of optimization cells in
the critical path has to be replaced by low Vt cells which are faster.
If the optimization target is to meet timing then first use low Vt
cell library to achieve timing and then optimize leakage power using
high Vt cells.