DFT

1. Introduction to Testing

1.1. Purpose of  DFT

1.2. Controllability and Observability

1.3. Pros and Cons of DFT

2. CMOS Failures

2.1. Stuck at Faults Modeling

            2.2. Single Stuck at models

2.3. Limitations of Combinational Logic Testing

            2.4. Determining Fault Coverage

            2.5. Fault Simulation

3. Automatically Generating Test Patterns

            3.1. Random pattern generation

3.2. Deterministic pattern generation

4. Testing Sequential Elements Using Scan

            4.1. Scan Shift Mode

            4.2. Scan Capture Mode

5. Internal Full Scan

             5.1. Muxed Scan

5.1.1.  Characteristics of Multiplexed Flip-Flop Scan Style

             5.2. Clocked Scan

5.2.1. Characteristics of Clocked-Scan Scan Style 

             5.3. Test Port Requirements

             5.4. Disadvantage of Scan Insertion

6. Boundary Scan – JTAG

             6.1. The Boundary-Scan Cell

                       6.1.1. Boundary Scan Cell Parallel Mode of Operation

                       6.1.2.  Boundary Scan Cell Serial Mode of Operation

             6.2. Test Access Port (TAP) Controller

             6.3. Boundary Scan Architecture Registers

                        6.3.1. Instruction Register

                        6.3.2. Bypass Register

                        6.3.3. Device Identification Register

                        6.3.4. Boundary Scan Register

              6.4. Basic Boundary Scan Cell

              6.5. Boundary Scan Design Flow

              6.6. Boundary-Scan Description Language (BSDL)

7.0.  BIST - Built In Self Test

7.0.1. Advantages of BIST

7.0.2. Disadvantages of BIST

7.0.3. Prequisites to BIST insertion

7.2. Types of BIST techniques

7.2.1. Logic BIST (LBIST)

7.2.2. Memory BIST (MBIST)

8. DFT Design Rule Check (DFT-DRC)

             8.1. Asynchronous Set/Reset Signals

             8.2. Generated clocks

             8.3. Gated Clocks

             8.4. Combinational Feedback Loops

             8.5. Bi-Directional I/O Ports

             8.6. Tri-State buses

9. Outputs from DFT

References:

[AGB] Essentials of Electronic testing, V D Agarwal and M L Bushell

[ABR] Digital System testing and Testable Design, M Abramovici et all

[FUJ] Logic Testing and Design for Testability, H Fujiwara

[SYN] Synopsys DFT Compiler User Guide

[CAD] Cadence RTL-Compiler DFT User Guide

[BEN] Boundary Scan Tutorial, Dr R G Ben Bennetts, ASSET InterTech Inc, www.dft.co.uk

(Now broken); available at below link:

http://fiona.dmcs.pl/~cmaj/JTAG/boundaryscan_tutorial.pdf

http://fiona.dmcs.pl/~rkielbik/nid/IEEE_1149_JTAG_and_Boundary_Scan_Tutorial.pdf

[SIL] http://www.siliconfareast.com/bist.htm (now broken); available at below link:

http://web.archive.org/web/20140213001512/http://www.siliconfareast.com/bist.htm

[UBC] http://courses.ece.ubc.ca/578/notes2.pdf