Synthesis

1.      Introduction to ASIC - SoC Design




History of VLSI Design

1. Introduction to ASIC - SoC Design

1.1.   IP Core Types

1.1.1. Soft Cores (RTL format)

1.1.2. Firm Cores (netlist format)

1.1.3. Hard Cores (GDSII format)

1.2. SoC Design Issues

 2.      IC Design Methodologies

2.1 Full Custom IC Design

2.2.Semi-customIC Design

2.2.1 Standard cell based ASIC design

2.2.2. Gate arrays

2.2.2. FPGA

2.3. Standard Cell ASIC Vs GateArray Vs FPGA

2.4. FPGA vs. ASIC

2.4.1 FPGA Design Advantages

2.4.2. FPGA Design Disadvantages

2.4.3. ASIC Design Advantages

2.4.4. ASIC Design Disadvantages

3.     Overviewof Complete ASIC Design Flow

4.     MajorEDA Companies and their tools

5.     RTLCoding for Logic Synthesis

5.1.Synthesizable and Non-Synthesizable Verilog constructs

5.2.How hardware is infered?

5.2.1  Register inference

5.2.2 Mux Inference

5.2.3. Priority Encoder Inference

5.2.4. Combo Logics

5.2.5. if vs case

5.2.6. Proper partitioning for synthesis

5.2.7. FSM synthesis guidelines

5.2.8. Blocking vs non-blocking-race condition

5.2.9. Technology independent RTL coding

5.2.10. Pads separate from core logic

5.2.11. Clock logic guidelines

5.2.12. Reset logic guidelines

5.2.13. Registered outputs

5.2.14. Incomplete sensitivity list

5.2.15. Avoid latch inference

5.2.16. Use Constants

5.2.17. General Coding guidelines for ASIC synthesis

6.      ASIC Synthesisis

6.1.Synthesis definition, goals

6.2.Inputs and output from ASIC synthesis flow

6.2.1. Register Transfer Level (RTL) Representation

6.2.2. Constraints

6.2.3. Target Library

7.     Technologylibraries :.lib

7.1Logic Library

7.2 Basics of Logic Library (.lib)

7.2.1. Library group

7.2.2. Library level atributes

7.2.3. Environment Description

7.2.3.1. Scaling Factors:

7.2.3.2.Operating Conditions:

7.2.3.3.Wire Load Models:

7.2.4. Cell description

8.     Operatingconditions

8.1. Process Variation

8.2. Supply Voltage Variation

8.3. Operating Temperature Variation

9.     Wireload models

9.1. Wire load models for synthesis

9.1.1 Top:

9.1.2 Enclosed

9.1.3 Segmented

10.  DesignObjects

11.  Fundamentals of Timing

11.1.Timing paths

12.  Setup and hold time definition

12.1.Setup Time

12.2.Hold Time

13.  Setup and hold slack

13.1. Regto Reg path

13.2. Regto Output

13.3.Input to Output

13.4.Input to Register

14.  Constraints: Clock, Logical DRC, Area,Power

14.1. DRC constraints
14.2 Optimization constraints

14.3.Timing Constraints
14.4. Environmental constraints

14.5. Other Synopsys Design Constraints

15.  Process of logic synthesis: reading verilog, elaboration, synthesize

15.1. Provide search path and target technology library

15.2. Read HDL

15.3. Analyze

15.4. Elaborate

15.5. Linking

15.6. Read Constraints

15.7. Compile or Synthesize Methodology and Optimizations

15.8. Synthesize optimiization

15.8.1. Architectural(RTL) Optimization (technology independent optimization)

15.8.2. Logic-Level Optimization (tech independent optimization)(Global Focus Mapping)

15.8.3. Gate-Level Optimization (Incremental Optimization (IOPT))

16.  Synthesis Strategies for Designs : top-down, bottom-up

16.1. Top-Down Synthesis

16.2. Bottom-Up Synthesis

17.  How to improve synthesis optimization results?

17.1. Creating Path Groups

17.2. Ungrouping Hierarchies on the Critical Path

17.3. Optimizing Across Hierarchical Boundaries

18.  Outputs from Synthesis

References

[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005

[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009

[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009