Verilog

Verilog Tutorial

• Verilog HDL-Modules
• Verilog HDL-Ports
• Verilog HDL: Operators, Number Specification, Underscore Characters, Strings, Identifiers and Keywords, Escaped Identifiers
• Verilog HDL: Expressions, Operators and Operands
• Verilog HDL: Data Types
• Verilog HDL: Hardware Description Using Basic Logic Gates
• Verilog HDL: Procedural Continuous Assignments
• Verilog HDL: Procedural Assignments
• Verilog HDL: Procedural Timing Controls
• Verilog HDL: Conditional Statements
• Verilog HDL: Parellel Blocks
• Verilog HDL: Generate Blocks
• Verilog HDL: Gate Level Modeling
• Verilog HDL: Behavioural Modeling
• Verilog HDL: Behavioural Description of ALU
• Verilog HDL: Behavioural Modeling: 8-Bit Ring Counter, 8-Bit Adder
• Verilog HDL: Functions And Tasks
• Verilog HDL: Usefull Modelling Techniques
• Verilog HDL: System Tasks, File Related Operations, Compiler Directives
• Verilog HDL: Timing and Delays In Verilog
• Verilog HDL: Switch-level Modeling
• Verilog HDL: User-Defined Primitives(UDP)
• Verilog HDL: Test Bench
• Verilog HDL: Test Bench for 4-Bit Adder
• Verilog HDL: Test Bench for 4 bit Counter
• RTL Coding for Logic Synthesis
  
  
   
  

  References:

[1]IEEE Std 1364™-2005, IEEE Standard for Verilog® Hardware Description Language By IEEE

[2]Verilog HDL By Samir Palnitkar