Verilog HDL: Data Types

Value Set:
                           ---> Four values  to model the functionality

                           ---> Eight strengths of real hardware

    Value level--------- Condition in hardware circuits

            0 ------------- > Logic zero, false condition
            1 ------------- > Logic one, true condition
            X ------------ > Unknown logic value
            Z ------------- > High impedance ,floating state


  • Represent connection between hardware elements ; is a datatype; not a keyword
  • Nets are declared primarily with the keyword ‘wire’
  • Default value is ‘z’
  • Exception : ‘trireg’ net,which defaults to x


           wire a;
           wire b,c;
           wire d=1’b0     //Net d is fixed to logic value zero at declaration


  • Represent data storage element
  • Retain value until another value is placed onto them
  • Keyword is ‘reg’


            reg reset;          //declare a variable reset that can hold its value

Registers can also be declared as signed variables


             reg signed[63:0] ; //64 bit signed value


Nets or reg (multiple bit widths) data types can be declared as vectors

Default is scalar (1-bit)

Eg :

       wire a;                                         //scalar net variable;default

       wire [7:0] bus;                            //8 bit bus

       wire [31:0] bus A,bus B,bus C;  //3 buses of 32 bit width

       reg clock;                                    //scalar register; default

       reg [0:40] virtual_addr;              //vector register. Virtual address 41 bits wide

// 0:always MSB ; 40:always LSB

Vector Part Select:
It is possible to address bits or parts of vectors.


        busA[7]                   //bit 7 of vector bus A

        bus[2:0]                  //three LSBs of vector bus

        virtual_addr[0:1]    //two MSBs of vector virtual_addr

 Variable Vector Part Select:


       reg[255:0] data 1;         //Little endian notation

       byte = data1[31-:8];      //starting bit=31,width=8=>data[31:24]

       byte = data[24+:8];       //starting bit =24, width=8=>data[31:24]


Default width is the host machine word size


         integer counter;                    //general purpose variable used as a counter


  • Can be in decimal notation(eg: 3.14)
  • Can be in scientific notation(eg: 3e6)
  • No range declaration possible
  • Default value is zero


          real delta;           //define a real variable


  • A special time register data type is used in verilog to store simulation time
  • Width is application specific ;but atleast 64 bits
  • The system function ‘$time’ is invoked to get the current simulation time
  • The simulation time is measured in terms of simulation seconds

Eg :

       time save_sim_time;                 //define a time variable save_sim_time

       initial save_sim_time= $time;  //save the current simulation time


  • Allowed for reg, integer, time, real, realtime and vector
  • Multidimensional arrays are also allowed
  • Arrays are accessed by []


      integer count[0:7] ;         //an array of 8 count variables

      reg bool[31:0] ;              //array of 32 one-bit Boolean register variables

      time chk_point[1:100];   //array of 100 time checkpoint variables

      reg [4:0] port_id[0:7];    //array of 8 port_ids; each port_id is 5 bits wide


  • Memories are modeled as a one-dimensional array of registers
  • Each word can be one or more bits

Eg :

      reg memory_1_bit[0:1023];           //memory memory_1_bit with 1K 1-bit words

      reg[7:0] memory_byte[0:1023];    //memory memory_byte with 1K 8-bit words(bytes)

      memory_byte[511]                        //fetches 1 byte word whose address is 511


  • Constant definitions


         parameter part_id =5;                        //defines a constant port_id

         parameter cache_line_width=256;    //constant defines width of cache line

         parameter signed [15:0] width;         //fixed sign and range for parameter width

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