12 November 2011

Verilog HDL-Ports

Ports

  • Ports provide the interface by which a module can communicate with its environment. (This is how technically it is defined by famous authors !!)
  • Also referred to as terminals. (As per Verilog terminology)

Eg :

module fulladd4(sum,c_out,a,b,c_in); //module with a list of ports

module top;                                        //No list of ports, top level module in simulation



Port Declaration

Keyword             Types of port

input -------------- input port

output ------------- output port

inout -------------- bidirectional port

  • All port declarations are implicitly declared as ‘wire

ANCI C Style Syntax

We define a module in ANCI C style syntax as well.

Eg :-

module fulladd4(output reg [3:0] sum, output reg c_out, input [3:0] a, b, input c_in);

     -------------------------------- 
     -------------------------------- 
      
     -------------------------------- 
     -------------------------------

endmodule

Here,

output reg [3:0] sum  ==> represents that “sum” is a 4 bit ( 0 to 3 being bits) output register.

input [3:0] a              ==> “a” is 4 bit (0 to 3 bit) wire;

In both cases 0th bit is LSB whereas 3rd bit is MSB.

Ports of type ‘input’ and ‘inout’ can’t be declared as ‘reg’ because ‘reg’ variables stores values.

Port Connection Rules

Inputs

  • Internally input ports must always be of the type ‘wire’.
  • Externally , the inputs can be connected to a variable which is a ‘reg’ or a ‘wire’.

Outputs

  • Internally , output ports can be of the type ‘reg’ or ‘wire
  • Externally they must always be connected to a ‘wire’. They can’t be connected to a reg.

Inouts

  • Internally inout ports must always be of the type ‘wire
  • Externally inout ports must always be connected to a ‘wire

Width Matching

It is legal to connect internal and external items of different sizes when making intermodule port connections. However, a warming is typically issued that the widths do not match.


Unconnected Ports

Unconnected ports are legal.

Eg.: fulladd fa0 (sum, , A, B, C_in);     //output port C_out is unconnected.

References
  • IEEE Standard for Verilog® Hardware Description Language, IEEE Std 1364™-2005
  • IEEE Standard Verilog® Hardware Description Language, IEEE Std 1364-2001
  • Samir Palnitkar, Verilog HDL A Guide to Digital Design and Synthesis, Second Edition
  

1 comment:

  1. Is and4x4 is equal to nand4x1 + inv1x4 ??
    if not why
    pls reply...
    thank u

    ReplyDelete

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