Static Timing Analysis Tutorials
Introduction to STA
- q What is Static Timing Analysis (STA)?
- q STA vs DTA
- q STA vs SPICE
- q Advantages of Static Timing Analysis
- q Disadvantages of Static Timing Analysis
- q STA Flow
- q Inputs to STA Flow
- q STA Tools
- q Summary
Delays in ASIC Design
- q Transition Delay
- q Propagation Delay
- q Gate Delay –Cell Propagation Delay
- q How gate delay is calculated?
- q Non Linear Delay Models - NLDM
- q NLDM - Two dimensional model
- q Net Delay
- q Net Parasites
- q Capacitance
- q Resistance
Interconnect Delay Models
- q Lumped Capacitor Model
- q Lumped RC Model
- q Elmore Delay Model
- q Distributed RC model
- q Transmission Line Model
- q Wire Load Models
- q Wire load models for synthesis
- q Pre Layout Vs Post Layout Net Delays
Clock Definitions
- Rising and falling edge of the clock
- Capture Clock Edge
- Launch Clock Edge
- Skew
- Local skew
- Global skew
- Positive Skew
- Negative Skew
- Uncertainty
- Pre-layout and Post-layout Uncertainty
- Clock latency
- Pre CTS Latency and Post CTS Latency
- Source Delay or Source Latency
- Network Delay (latency) or Insertion Delay
- Jitter
- Multiple Clocks
- Asynchronous Clocks
- Gated clocks
- Generated clocks
- Virtual Clocks
The Story of Setup and Hold Time
- q Setup Time
- q Hold Time
- q Metastability
- q Timing Path
- q Different Timing Paths
- o Input to Reg
o Reg to Reg
o Reg to Output
- q Clock path
- q Data path
- q Launch path
- q Capture path
- q Data Arrival Time Data Required Time
- q Slack
- q Report_timing
- q Setup Slack
- q Hold Slack
Timing Analysis in Different
paths
q Setup Analysis of Reg to Reg
q Maximum frequency calculation examples
q Setup Analysis of Input to Reg
q Setup Analysis of Reg to Output
q Hold Analysis of Reg to Reg
q Hold Analysis of Input to Reg
q Hold Analysis of Reg to Output
Analyzing Reports: report_timing
- q Start and End Point
- q Data Arrival
- q Data Required
- q Slack
- q Hold Slack
Timing Exceptions
q Multicycle path
q False path
q Feedthrough Path
Part 2. Advanced STA
Checks
q Clock gating check
q Feedback loops
q Case analysis
q Minimum pulse width check
q Recovery Check
q Removal Check
q Analysis Modes
q Data to Data Checks
q Multiple Clocks per Register
q Derived Clocks
q Netlist Editing
q Report_clock_timing
q Clock Reconvergence Pessimism (CRPR)
q Worst-Arrival Slew Propagation
q Debugging Delay Calculation
Back Annotation
- q Standard Delay Format- SDF
- q DSPF: Detailed Standard Parasitic File
- q Reduced Standard Parasitic File (RSPF)
- q Standard Parasitic Exchange Format (SPEF)
- q STA with Backannotation
- q Extraction
SI Analysis
q What is SI
q What is Crosstalk?
q How Crosstalk happens?
q Impact of Crosstalk
q Crosstalk Noise
q Impact of crosstalk noise on setup and hold
q Crosstalk Delay
q Impact of crosstalk delay on setup and hold
q Crosstalk Solutions
q IR Drop
q Electron Migration
Timing Models
q Quick Timing Model (QTM)
q Extracted Timing Model (ETM)
q Interface Logic Model (ILM)
Stamp
Model
References
[2] David Blaauw, Kaviraj Chopra, Ashish Srivastava and Lou Scheffer,
“Statistical Timing Analysis: From basic principles to state-of-the-art.”
Transactions on Computer-Aided Design of Integrated Circuits and Systems
(T-CAD), invited review article, to appear.
[3] Andrew B. Kahng, Bao Liu and Xu Xu, “Statistical Timing Analysis in the
Presence of Signal-Integrity Effects,” IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems, vol. 22, no.10, Oct. 2007.
[5] Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswaran and Chandu
Visweswariah, “Criticality Computation in Parameterized Statistical Timing,”
DAC 2006: 63-68.
[8] A. Nardi, E. Tuncer, S. Naidu, A. Antonau, S. Gradinaru, T.Lin and J. Song,
“Use of Statistical timing Analysis on Real Designs” Proceedings of the IEEE
Design, Automation & Test in Europe Conference & Exhibition, pp. 1-6,
April 2007.
[9] Agarwal, A. Blaauw, D. Zolotov, V. Sundareswaran, S. Min Zhao Gala, K. and
Panda, R., “Statistically Delay computation considering spatial correlations,”
Proceedings of the ASP-DAC 2003, pp.271-276, Jan 2003.
[10] Aseem Agarwal, David Blaauw and Vladimir Zolotov, “Statistical Timing
Analysis for Intra-Die process Variations with spatial correlations” IEEE
Transactions on Computer-Aided Design, pp. 900-907, Nov 2003.
[11] Aseem Agarwal, David Blaauw and Vladimir Zolotov, “Statistical Clock Skew
Analysis Considering Intra-Die Process Variations,” IEEE Transactions on
Computer-Aided Design, vol. 23, no. 8, pp. 1231-1242, Aug, 2004.
[12] Ayhan Mutlu, Kelvin J. Le, Mustafa Celik, Dar-sun Tsien, Garry Shyu, and
Long-Ching Yeh, “An Exploratory Study on Statistical Timing Analysis and
Parametric Yield Optimization,” Proceedings of the 8th International Symposium
on Quality Electronic Design, pp. 677-684, 2007.
[13] Robert B.Hitchcock, Sr, Gordon L. Smith, David D. Cheng, “Timing Analysis
of Computer Hardware,” IBM Journal, vol. 26, no. 1, Jan 1981.
(14) "Investigation of typical 0.13 μm CMOS technology timing effects in a
complex digital system on-chip", www.diva-portal.org/diva/getDocument?urn_nbn_se_liu_diva-2118-1__fulltext.pdf
[BHA] J. Bhasker •
Rakesh Chadha, “Static Timing Analysis
for Nanometer Designs A Practical Approach”, Springer, 2009
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