The doubt why is set up and hold in flip-flop always lingers in my mind. Being a digital design engineer, i should be able to go beneath transistor and convince myself the existence of setup delay and hold delay. I know metastability state of the flip flop or charging or discharging of capacitor on a CMOS, upon which all the gates, flip flops are built. When i say "i know metastability" i may know about its standard definition as per data book. If i advent into getting answer to "why metastability", i believe i must be able to understand setup time and hold time.
Let me try to dig myself. What i know? Flip flop is combination of 2 latches, and latch is level triggered. One is positive level triggered and another in negative level triggered. If so whatever data sent to two latches will be launched or captured on different edges. Then why metastability? Why set up time? Why hold time?
So how two level triggered latches form an edge triggered flop? Let me get in to the latch. After all how it works? Say one input is given...then when can i expect the output data? Is it immediately ? or does it take some time ?
If i remember working of simple SR latch from several theory classes and text books i know that any latch output doesn’t stabilize immediately. Output changes to intermediate values of 0 (or 1) then 1 (or 0) then finally it gets settles at 0 (or 1). It used to take 2 or 3 looping of data between NOR (or NAND ) gates.
So in this way it takes 2-3 data cycles....right....This must happen for both latches of flop. Hence this must take some time, may be in nano second or pico second, but it consumes some time !
Now, from the working principle of Master slave flip flop, i know that both latches won’t work together. Because i have arranged flop circuit such away that slave follows master. It means to say that when master latches the data slave sleeps, then slave follows master. Or in other words, slave releases the data which is latched earlier by the master. As i understood earlier, to latch the data, master takes 2-3 cycle. Same should be the story for slave.
Now let me extend my imagination to the next horizon.
To a flop which is exclusively designed as edge triggered with basic gates itself, may be NOR or NAND based, or may be based on CMOS full custom circuit, same of 2-3 cycle delay applies here as well. All that happens is those 2-3 cycles to stabilize data which is coming in and going out !
I should analyze practical conditions of latching the data.
Considering one internal data cycle is completed in logic gate,data is not yet stabilized within this latch. If i allow one more input to enter at the same time what will happen to that data which was under process? Naturally latch may start processing new input data or may go to unknown loop state that i think i call as metastable state ! Poor latch, it must have completely confused, whether to drop the catching of present data or should i try to catch new one? I am the boss and hence i, as a designer of latch, has instructed latch to to both, to process present data (so that it can catch it and memorize it), then look for new one. As a duty bound soldier latch will try to do both.
Same applies for data that was already latched but about to leave out of the latch. These two timing delay requirements ultimately constitute setup and hold; hold time is for time required for data to come out while setup for data to get latched. Hence, i believe, hold is always related with launch clock whereas setup is related with capture clock.
So, what I can i understand is i don’t need a reference for hold since it’s already in flop. That’s why for hold analysis, clock period is always considered as 0ns, which virtually turns out to be no clock. ( or..."hold is not dependent on clock"). This is not always true. There are exceptional cases where data is not launched at 0ns with respect to capture clock. These kind of situations should be dealt separately.
Always i must remember that flop has latch structure, this means to say, when one latch works another doesn't do any work. So if i consider register to register path, when one is launching data next one is ready to receive data. That’s all ! It continues like that way throughout the digital circuit. When first one is receiving next flop is ready to launch...and so on. To summarize, it takes one clock cycle to complete the launch or capture. That’s why we always use terms such as present data, previous data when dealing with data flow through flip flop so that i can understand the delay introduced by the flop (due to its latch architecture) which i technically termed it as setup time and hold time.
As per the definition, data should be stable at input before clock pulse ticks at the clock pin of the flip flop. I understand from the definition that data at the input should have completed the process of 2-3 cycle interchanging values at the receiving gates section of the latch to settle down to a known value. By any means, if clock is faster (or data is slower in its arrival at input), then it can tick at at the time when data might have completed its 1 or 2 cycle interchanging state. Then i am sure any one of these intermediate value can get latched, which may not the actual intended original input data.
For hold, definition is time for which data should be stable after clock edge. Once the clock edge ticks data present within latch tries to go out. I know this takes another 2-3 cycle intermediate values within latch and settle to known value at the output pin of the flip flop. Imagining that output pin is connected to input of another flip flop and there is no combinational circuit in between them, lets assume that delay is zero or very less. In this case intermediate value can immediately reflect at the input of receiving flip flop, which is functionally fatal error. Introduce a delay element which is more than 2-3 cycle delay time (i.e. hold time), then delay element provides sufficient time for the data to settle to known value.
Looking into these aspects minimum period for the clock can't be less than the addition of setup time and hold time. if clock period becomes lesser than this, i am sure flip flop will fail.
But i should be cautious in understanding that every capture flop becomes launch flop for new data to be launched. So we need to make sure that combinational delay is enough so that new data launched doesn’t kill the data which is already available within flop. And hence hold check is carried out for clock edge which is one lesser than (or previous to) setup check. Or in other words, setup check for present data which is traveling, hold for new (future) data. Present data should reach the capture flop input before capture clock reaches there.(Setup check). New data shouldn't reach too fast to capture flop so that present data doesn't corrupt.
Well...after all these literature exercise i must agree that i don't want all jargons to implement a practical design. What i need is basic understanding of setup time, hold time and how this affects or controls the timing of a timing path. It would be nice if i can fix setup and hold violations by adjusting rest of the parameters such as skew, latency and jitter.