The power consumed by the subthreshold currents and by
reverse biased diodes in a CMOS transistor are
considered as leakage power.The leakage power of a
CMOS logic gate does not depend on input transition or
load capacitance abd hence it remains constant for a
The subthreshold current always flow from source to
drain even if the gate to source voltage is lesser
than the threshold voltage of the device. This happens
due to the carier diffusion between the source and
drain regions of the CMOS tranistor in weak inversion.
When gate to source voltage is smaller than but very
close to threshold voltage of the device then
subthreshold current becomes significant.
How to minimize subthreshold leakage?
A increase in the threshold voltage of the device
keeps the Vgs of the NMOS transistor safely below the
Vt,n. This is the case for logic zero input. For the
logic one input increase in the threshold voltage of
the device keeps the Vgs of the PMOS transistor
safely below the Vt,p.
Reverse Biased Diode Current
Parasitic diodes formed between the diffusion region
of the transistor and substrate consume power in the
form of reverse bias current which is drwn from the
I inverter when input is high NMOS transistor is ON
and output voltage is discharged to zero. Now between
drain and the n-well a reverse potential difference of
Vdd is established whcih causes diode leakage through
the drain junction.
The n-well region of the PMOS transistor w.r.to.
p-type sustrate is also reverse biased. This also
leads to leakage current at the N-well junction.
The reverse current can be mathematically expressed
Vbias-->reverse bias voltage across the junction
Js-->reverse satuartion current density