Low Power Techniques - Presentation

Low Power Techniques

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Low Power Design Techniques

Michael Keating et al. [1] lists several low power techniques to tackle the dynamic and static power consumption in modern SoC designs. Dynamic power control techniques include clock gating, multi voltage, variable frequency, and efficient circuits. Leakage power control techniques include power gating, multi Vt cells. Common methods supported by EDA tools include clock gating, gate sizing, low power placement, register clustering, low power CTS, multi Vt optimization.

Some of the low power techniques in use today are listed in below table.

Different Low Power Techniques [3]

Trade-offs associated with the various power management techniques [2]

Above table summarizes trade-offs associated with different power management techniques. Power gating and DVFS demand large methodology change whereas multi vt and clock gating affect least. Unless large leakage optimization is not necessary it is always beneficial to go with either multi vt or clock gating techniques. Based on the design complexity and requirements combination of any low power techniques can be adopted. Multi vt optimization along with the power gating is found to be efficient in some of the complex designs. Advanced improvements in the implementation (i.e. fabrication) technology has allowed substrate biasing techniques to be used heavily as it does not pose any architectural and design verification challenges and also provides high leakage reduction.

References

[1] Michael Keating, David Flynn, Robert Aitken, Alan Gibsons and Kaijian Shi, “Low Power Methodology Manual for System on Chip Design”, Springer Publications, NewYork, 2007, www.lpmm-book.org, 4/9/2007

[2] Creating Low-Power Digital Integrated Circuits – The Implementation Phase, Cadence, 2007

[3]Godwin Maben, "Low Power Techniques in Use Today"

Leakage Power

Leakage Power

The power consumed by the subthreshold currents and by
reverse biased diodes in a CMOS transistor are
considered as leakage power.The leakage power of a
CMOS logic gate does not depend on input transition or
load capacitance abd hence it remains constant for a
logic cell.


Subthreshold Current

The subthreshold current always flow from source to
drain even if the gate to source voltage is lesser
than the threshold voltage of the device. This happens
due to the carier diffusion between the source and
drain regions of the CMOS tranistor in weak inversion.

When gate to source voltage is smaller than but very
close to threshold voltage of the device then
subthreshold current becomes significant.


How to minimize subthreshold leakage?

A increase in the threshold voltage of the device
keeps the Vgs of the NMOS transistor safely below the
Vt,n. This is the case for logic zero input. For the
logic one input increase in the threshold voltage of
the device keeps the Vgs of the PMOS transistor
safely below the Vt,p.

Reverse Biased Diode Current

Parasitic diodes formed between the diffusion region
of the transistor and substrate consume power in the
form of reverse bias current which is drwn from the
power supply.



I inverter when input is high NMOS transistor is ON
and output voltage is discharged to zero. Now between
drain and the n-well a reverse potential difference of
Vdd is established whcih causes diode leakage through
the drain junction.

The n-well region of the PMOS transistor w.r.to.
p-type sustrate is also reverse biased. This also
leads to leakage current at the N-well junction.

The reverse current can be mathematically expressed
as,

Ireverse=A.Js.(exp(q.Vbias/kT)-1)

where,
Vbias-->reverse bias voltage across the junction
Js-->reverse satuartion current density
A-->junction area

Short circuit power

Short circuit power

Consider an exaple of inverter. During switching both
NMOS and PMOS transistors in the circuit conduct
simultaneously for a short amount of time. This forms
direct current path between the power supply and the
ground. This current has no contribution towards
charging of the output capacitance of the logic gate.

When the input rising voltage exceedds the threshold
voltage of NMOS transistor, it starts conducting.
Similarly untill input voltage reaches Vdd-|Vt,p| PMOS
transistor remains ON. Thus for some time both
transistors are ON. Similar event causes short circuit
current to flow when signal is falling. Short circuit
current terminates when transition is completed.

Assuming symmetric inverter with Kn=Kp=K and
Vt,n=|Vt,p|=Vt and very small capacitive load and both
rise and fall times are same we can write,

Pavg(short circuit)=1/12.k.Tow.fclk.(Vdd-2Vt)3.

Thus short circuit power is directly proportional to
rise time, fall time and k.

Therefore reducing the input transition times will
decrease the short circuit current component. But
propagation delay requirements have to be considered
while doing so.
======================================================
Reference:

Sung Mo Kang and Yusuf Leblebici, CMOS digital
integrated circuits-analysis and design, Tata McGraw
hill, third edition, 2003
======================================================

Dynamic (switching) power

As we seen in earlier blog the average power consumed
by the CMOS circuit can be devided into three
different components[1]. They are:

1)Dynamic (switching)power consumption

2)Short circuit power consumption

3)Static (Leakage) power consumption
==========================================================================

Dynamic (switching) power dissipation

As the name indicates it occurs when signals which
goes through the CMOS circuits change their logic
state. At this moment energy is drawn from the power
supply to charge up the output node
capacitance.Charging up of the output capacitnce
causes transition from 0V to Vdd.Considering an
inverter exaple power drawn from the power supply is
dissipated as heat in pMOS transitor.
On the other hand charge down process causes NMOS
transistor to dissipate heat.

Output capacitance of the CMOS logic gate consists of
below components:

1)Output node capacitance of the logic gate: This is
due to the drain diffusion region.

2)Total interconnect capacitance: This has higher
effect as technology node shrinks.

3)Input node capacitance of the driven gate: This is
due to the gate oxide capacitance.

To find the avearage power energy required to charge
up the output node to Vdd and charge down the total
output load capacitance to ground level is integrated.
Applied input periodic waveform having its period T is
assumed to be having zero rise and fall time. Note
that average power is independent of transistor size
and characteristics.

Internal power

This is the power consumed by the cell when an input
changes, but output does not chnage[2]. In
logic gates not every change of the current running
through an input cell necessarily leads to a change in
the state of the output net. Also internal node
voltage swing can be only Vi which can be smaller than
the full voltage swing of Vdd leading to the partial
voltage swing.

======================================================
How to reduce dynamic power?

1)reduce power supply voltage Vdd
2)reduce voltage swing in all nodes
3)reduce the switching probabilty (transition factor)
4)reduce load capacitance

=======================================================
Reference:

[1] Sung Mo Kang and Yusuf Leblebici, CMOS digital
integrated circuits-analysis and design, Tata McGraw
hill, third edition, 2003
[2]Astro User Guide, Version X-2005.09, September 2005
=======================================================

Different Types of Power Consumption in CMOS Circuits

Different Types of Power Consumption in CMOS Circuits

The average power consumed by the CMOS circuit can be devided into three
different components[1]. They are:

1)Dynamic (switching)power consumption

2)Short circuit power consumption

3)Static (Leakage) power consumption

Detail discussion on these topics we will see in coming blogs !

=======================================================
Reference:

[1] Sung Mo Kang and Yusuf Leblebici, CMOS digital integrated circuits-analysis and design, Tata McGraw hill, third edition, 2003
=======================================================