Consider an exaple of inverter. During switching both
NMOS and PMOS transistors in the circuit conduct
simultaneously for a short amount of time. This forms
direct current path between the power supply and the
ground. This current has no contribution towards
charging of the output capacitance of the logic gate.
When the input rising voltage exceedds the threshold
voltage of NMOS transistor, it starts conducting.
Similarly untill input voltage reaches Vdd-|Vt,p| PMOS
transistor remains ON. Thus for some time both
transistors are ON. Similar event causes short circuit
current to flow when signal is falling. Short circuit
current terminates when transition is completed.
Assuming symmetric inverter with Kn=Kp=K and
Vt,n=|Vt,p|=Vt and very small capacitive load and both
rise and fall times are same we can write,
Thus short circuit power is directly proportional to
rise time, fall time and k.
Therefore reducing the input transition times will
decrease the short circuit current component. But
propagation delay requirements have to be considered
while doing so.
Sung Mo Kang and Yusuf Leblebici, CMOS digital
integrated circuits-analysis and design, Tata McGraw
hill, third edition, 2003