Low Power Techniques: Multi Voltage (Vdd)

Dynamic power is directly proportional to power supply. Hence
naturally reducing power significantly improves the power
performance.At the same time gate delay increases due to the decreased
threshold voltage.


High voltage can be applied to the timing critical path and rest of
the chip runs in lower voltage. Overall system performance is
maintained.


Different blocks having different voltage supplies can be integrated
in SoC. This increases power planning complexity in terms of laying
down the power rails and power grid structure. Level shifters are
necessary to interface between different blocks.


Related Articles

Low Power Techniques: Clock Gating

Multiple Voltage ASIC/SoC Designs: Classification

Multiple Voltage Designs: Timing Issues

Multiple Voltage Designs: Power Planning Issues



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