24 September 2007

Low Power Techniques: Clock Gating

Clock buffers consume more than 50 % of dynamic power. Hence it is
good design idea to turn off the clock when it is not needed.Automatic
clock gating is supported by modern EDA tools. They identify the
circuits where clock gating can be inserted.

Specific clock gating cells are required in library to be utilized by
the synthesis tools. Availability of clock gating cells and automatic
insertion by the EDA tools makes it simpler method of low power
technique. Advantage of this method is that clock gating does not
require modifications to RTL description.

Related Articles

Low Power Techniques: Multi Voltage (Vdd)

Multiple Voltage ASIC/SoC Designs: Classification

Multiple Voltage Designs: Timing Issues

Multiple Voltage Designs: Power Planning Issues

No comments:

Post a Comment

Your Comments... (comments are moderated)