Verilog HDL: Gate Level Modeling

Gate Level Modeling:

à For small number of gate designs;

à Feedbackless structure;

à Used in top level to integrate the design.

Gate –Level Modeling (Structural Modeling):

à mainly includes instantiation of built-in primitives.

à and,nand,or,nor etc

Verilog HDL: Generate Blocks

Generate   Blocks :

--> keywords  :  generate ,  endgenerate

--> Generated   instantiations  can  be  one  or  more  of  the  following  types :

                               --> modules

                               --> user  defined  primitives

                               --> gate  primitives

                                --> continuous  assignments

                                --> ’initial’  and  ‘always’ blocks

There  are  3  methods  to  create  generate  statements :

Verilog HDL: Parellel Blocks

Parallel  Blocks :fork, join:

Keywords : fork    

                     Join

--> statements  in  parallel  block  are  executed   concurrently

--> ordering  of  statement  is  controlled  by  the  delay  or  event  control  assignment  to  each  statement

--> if  delay  or  event  control  is  specified, it  is  relative   to  the  time  the  block  was  entered.

Eg :   

Verilog HDL: Conditional Statements

Conditional  Statements:  (same  as  C)

Multiway  Branching :

Case  statement   syntax :

case (expression)

Alternative  1 : statement 1;

Alternative 2 : statement 2;

Alternative 3 : statement 3;

default : default_statement;

endcase

 

Verilog HDL: Procedural Timing Controls

Procedural Timing   Controls

·         3  methods :   

o   Delay-based  timing  control

o   Event-based  timing  control

o   Level-sensitive  timing  control

Verilog HDL: Procedural Assignments

Procedural  Assignments :-

This  update  values  of  reg, integer,real or time variables.  The  value  placed  on  a  variable  will remain unchanged  until another  procedural   assignment  updates  the  variable  with  a  different  value.

The  lefthand  side  of  a  procedural  assignment  <lvalue>   can  be  one  of  the  following :

      reg, integer,real or time  register  variable  or  a memory  element

      bit  select  of  those  variables (eg : addr[0])

      part  select  of  those  variables (eg :  addr[31:16])

      concatenation  of  any  of  the  above

Verilog HDL: Procedural Continuous Assignments

à starts with a keyword “assign”

Characteristics of continuous assignments:

• The left hand side of an assignment must always be a scalar or vector net or a concatenation of scalar and vector nets. It can’t be a scalar or vector register.
• Continuous assignments are always active. The assignement  expression is evaluated  as soon as the one of the right hand side operands changes and the value is assigned to the left hand side net.
  

Verilog HDL: Hardware Description Using Basic Logic Gates

There are 14 logic gates and 12 switches predefined in the Verilog HDL to provide the gate- and switchlevel modeling facility.

Gate-Types:

• Supports basic logic gates as oredefined primitives.

• and, or, nand, nor, xor, xnor: These gates can have multiple inputs and 1 output.

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Verilog HDL: Data Types

Value Set:
                           ---> Four values  to model the functionality

                           ---> Eight strengths of real hardware

    Value level--------- Condition in hardware circuits

            0 ------------- > Logic zero, false condition
            1 ------------- > Logic one, true condition
            X ------------ > Unknown logic value
            Z ------------- > High impedance ,floating state

Verilog HDL: Expressions, Operators and Operands

Dataflow modeling in Verilog describes the design in terms of expressions, instead of primitive gates. ‘expressions,, ‘operators’ and ‘operands’ form the basis of Verilog dataflow modeling.

Arithmetic:

                            *       ---> Multiplication
                            /        ---> Division
                           +        ---> Addition
                           -         ---> Subtraction
                           %       ---> Modulo
                          **        ---> Power or exponent

Verilog HDL: Operators, Number Specification, Underscore Characters, Strings, Identifiers and Keywords, Escaped Identifiers

Operators:

Unary          : Precede the operand; always comes left of the operand. Eg: a=~b;
Binary         : Appear between two operands. Eg: a=b&&c;
Conditional : Have two separate operators that separate three operands. Eg: a=b?c:d;

 

Verilog HDL-Ports

Ports

• Ports provide the interface by which a module can communicate with its environment. (This is how technically it is defined by famous authors !!)
• Also referred to as terminals. (As per Verilog terminology)

Eg :

module fulladd4(sum,c_out,a,b,c_in); //module with a list of ports

module top;                                        //No list of ports, top level module in simulation

Verilog HDL-Modules

Verilog is a one of the famous Hardware Descriptive Languages (HDL). (VHDL is the other one). Verilog langauage syntax very well matches with C language syntax. This is big advantage in learning Verilog. Logic operators, data types, loops are similar to C. In addition to this certain data types which are necessary to describe a hardware are available in Verilog. For example, nets in a schematic or hardware design is refered here as ‘wire’. Flip-flops (or in general are called as registers) are defined as type ‘reg’.


“module”s are building block of Verilog. Consider any design represented by a block diagram with its inputs and outputs.

Fixing Transition Violation

Transition violations can be fixed by different methods based on the design situations.

 

They include:

 

• Up sizing the driver cell 
• Decreasing the net length by moving cells nearer or reducing long routed net 
• By adding buffers 
• By using existing spare cells as buffers 
• By splitting loads through buffers to reduce the fan out number (number of driven cells)