In normal mode of operation DFT circuits are not utilized. Hence direct timing analysis of the DFT enabled netlist considers DFT related circuits and generates wrong analysis. To overcome this drawback the tool has to be instructed to exclude DFT circuitry from timing analysis. For example, in the Systolic Array Matrix Multiplier design due to scan enable signal, very large –ve slack (-105) is predicted. This problem is tackled using command set_case_analysis 0 test_se. By doing this tool is informed not to consider the scan enable signal test_se for normal timing analysis. Corresponding correct timing report after the execution of this command is shown below.
Startpoint: reset (input port)
Endpoint: out_reg00_reg[2]
(rising edge-triggered flip-flop clocked by clock)
Path Group: clock
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
sam3 280000 cb13fs120_tsmc_max
Point Incr Path
-----------------------------------------------------------
clock (input port clock) (rise edge) 0.00 0.00
input external delay 0.40 0.40 r
reset (in) 0.00 0.40 r
U638/CIN (pc3d11) 0.95 1.35 f
U327/ZN (inv0d1) 0.25 1.59 r
………………………………… … ……………
out_reg00_reg[2]/D (sdnrq1) 0.00 4.19 f
data arrival time 4.19
clock clock (rise edge) 4.75 4.75
clock network delay (ideal) 0.90 5.65
clock uncertainty -0.47 5.18
out_reg00_reg[2]/CP (sdnrq1) 0.00 5.18 r
library setup time -0.19 4.98
data required time 4.98
-----------------------------------------------------------
data required time 4.98
data arrival time -4.19
-----------------------------------------------------------
slack (MET) 0.80
From the timing report it can be observed that slack of DFT enabled circuit has reduced.
The power report reports higher power consumption for DFT enabled circuit. Note that I/O pads are already inserted and with this consideration the total power is estimated as 110mW. Power estimation without I/O pads yields a value of 16mW. With the insertion of DFT circuits reported power is shown below.
****************************************
Report : power
-analysis_effort low
Design : sam3
Version: V-2004.06-SP1
Date : Mon Apr 23 16:26:09 2007
****************************************
Global Operating Voltage = 1.08
Power-specific unit information :
Voltage Units = 1V
Capacitance Units = 1.000000pf
Time Units = 1ns
Dynamic Power Units = 1mW (derived from V,C,T units)
Leakage Power Units = 1pW
Cell Internal Power = 284.3075 mW (99%)
Net Switching Power = 2.1465 mW (1%)
---------
Total Dynamic Power = 286.4540 mW (100%)
Cell Leakage Power = 38.3158 uW
It can be clearly observed that power consumption increased more than twice. Even though DFT circuits don’t contribute anything to normal functionality of the design, they consume static power. Hence when it comes to larger designs, keeping design trade-off in mind, DFT has to be implemented carefully.
It is very natural that DFT causes area overhead. From the previous post (Application of DFT technique) we have noticed that DFT improves testability. Thus the trade-off of testability and area and power are challenging issues for present ASIC designers.
Fault coverage of the DFT enabled design can be estimated using command estimate_test_coverage. The corresponding log data is shown below.
Starting test coverage estimation ...
12190 faults were added to fault list.
Uncollapsed Stuck Fault Summary Report
-----------------------------------------------
fault class code #faults
------------------------------ ---- ---------
Detected DT 12154
Possibly detected PT 0
Undetectable UD 36
ATPG untestable AU 0
Not detected ND 0
-----------------------------------------------
total faults 12190
test coverage 100.00%
-----------------------------------------------
Information: The test coverage above may be inferior
than the real test coverage with customized
protocol and test simulation library.
From the above data it can be observed that total 12190 faults are possible and all are testable making 100% fault coverage. But the tool informs that 100% coverage may not be practically possible.
Reference
[1] Himanshu Bhatnagar, Advanced ASIC chip Syntheis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[2] Design Compiler® User Guide, Version X-2005.09, September 2005
Related Articles
Synthesis Constraints
Optimization Methodology
Application of DFT technique
Showing posts with label Design For Test (DFT). Show all posts
Showing posts with label Design For Test (DFT). Show all posts
Application of DFT technique
DFT techniques provide controllability and observability. Automatic Test Pattern Generation (ATPG) is used for combinational design and DFT is used for sequential circuits.
Basically two methodologies are followed in the industry.
They are:
1. Scan DFT
2. Built In Self Test (BIST)
Under scan DFT two sub categories are available known as full scan and partial scan. Generally tools support only full scan DFT. Built in DFT compiler of Design Compiler provide multiplexed full scan DFT.
Two ways can be followed while inserting DFT elements to the design. The first one is to compile the design first and then insert scan elements. The second method is to insert scan elements to DFT and then compile.
To check whether design has any DFT rule violations dft_drc command is used. dft_drc check can be enabled by using commands set hdlin_enable_rtldrc_info true and set test_enable_dft_drc true. A test clock for DFT is generated using command create_test_clock clock waveform {25 50}. Period of the test clock is always greater than the original clock period. Total number of scan paths and methodology used are instructed using the command create_test_protocol. Longest chain length in a scan path can also be specified. As per power report, this constraint increases power consumption. insert_scan or insert_dft command converts all Flip Flops to scan registers.
Below is the log data from DFT compiler (in built in Design Compiler). The design synthesized is 3x3 Systolic Array Matrix Multiplier.
Information: Using default scan style 'multiplexed_flip_flop'. (TESTDB-279)
Loading db file '/home/Master_Files/Libraries/gtech.db'
Loading target library 'gtech'
Loading design ...
Starting rtldrc ...
Initializing rtldrc ...
Starting rule checks ...
Information: Scan style is 'multiplexed_flip_flop'. (TEST-1212)
Information: Starting test protocol creation. (TEST-219)
...reading user specified clock signals...
Information: Identified system/test clock port clock (25.0,50.0). (TEST-265)
...reading user specified asynchronous signals...
Loading test protocol
Loading target library 'cb13fs120_tsmc_max'
Loading target library 'cb13io320_tsmc_max'
Warning: IO pad 'pc3d10' is unusable: unknown logic function. (OPT-1022)
Warning: IO pad 'pc3d00' is unusable: unknown logic function. (OPT-1022)
Loading design 'sam3'
Pre-DFT DRC enabled
Information: Starting test design rule checking. (TEST-222)
...basic checks...
...basic sequential cell checks...
...checking for scan equivalents...
...checking vector rules...
...checking pre-dft rules...
-----------------------------------------------------------------
DRC Report
Total violations: 0
-----------------------------------------------------------------
Test Design rule checking did not find violations
-----------------------------------------------------------------
Sequential Cell Report
0 out of 467 sequential cells have violations
-----------------------------------------------------------------
SEQUENTIAL CELLS WITHOUT VIOLATIONS
* 467 cells are valid scan cells
From the above log data it can be observed that there are no DFT violations in the example design considered here. By default, multiplexed flip flop scan technique is used by the tool as seen in the above log data.
Reference
[1] Himanshu Bhatnagar, Advanced ASIC chip Syntheis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[2] Design Compiler® User Guide, Version X-2005.09, September 2005
Related Articles
Synthesis Constraints
Optimization Methodology
DFT enabled circuit analysis and fault coverage
Basically two methodologies are followed in the industry.
They are:
1. Scan DFT
2. Built In Self Test (BIST)
Under scan DFT two sub categories are available known as full scan and partial scan. Generally tools support only full scan DFT. Built in DFT compiler of Design Compiler provide multiplexed full scan DFT.
Two ways can be followed while inserting DFT elements to the design. The first one is to compile the design first and then insert scan elements. The second method is to insert scan elements to DFT and then compile.
To check whether design has any DFT rule violations dft_drc command is used. dft_drc check can be enabled by using commands set hdlin_enable_rtldrc_info true and set test_enable_dft_drc true. A test clock for DFT is generated using command create_test_clock clock waveform {25 50}. Period of the test clock is always greater than the original clock period. Total number of scan paths and methodology used are instructed using the command create_test_protocol. Longest chain length in a scan path can also be specified. As per power report, this constraint increases power consumption. insert_scan or insert_dft command converts all Flip Flops to scan registers.
Below is the log data from DFT compiler (in built in Design Compiler). The design synthesized is 3x3 Systolic Array Matrix Multiplier.
Information: Using default scan style 'multiplexed_flip_flop'. (TESTDB-279)
Loading db file '/home/Master_Files/Libraries/gtech.db'
Loading target library 'gtech'
Loading design ...
Starting rtldrc ...
Initializing rtldrc ...
Starting rule checks ...
Information: Scan style is 'multiplexed_flip_flop'. (TEST-1212)
Information: Starting test protocol creation. (TEST-219)
...reading user specified clock signals...
Information: Identified system/test clock port clock (25.0,50.0). (TEST-265)
...reading user specified asynchronous signals...
Loading test protocol
Loading target library 'cb13fs120_tsmc_max'
Loading target library 'cb13io320_tsmc_max'
Warning: IO pad 'pc3d10' is unusable: unknown logic function. (OPT-1022)
Warning: IO pad 'pc3d00' is unusable: unknown logic function. (OPT-1022)
Loading design 'sam3'
Pre-DFT DRC enabled
Information: Starting test design rule checking. (TEST-222)
...basic checks...
...basic sequential cell checks...
...checking for scan equivalents...
...checking vector rules...
...checking pre-dft rules...
-----------------------------------------------------------------
DRC Report
Total violations: 0
-----------------------------------------------------------------
Test Design rule checking did not find violations
-----------------------------------------------------------------
Sequential Cell Report
0 out of 467 sequential cells have violations
-----------------------------------------------------------------
SEQUENTIAL CELLS WITHOUT VIOLATIONS
* 467 cells are valid scan cells
From the above log data it can be observed that there are no DFT violations in the example design considered here. By default, multiplexed flip flop scan technique is used by the tool as seen in the above log data.
Reference
[1] Himanshu Bhatnagar, Advanced ASIC chip Syntheis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[2] Design Compiler® User Guide, Version X-2005.09, September 2005
Related Articles
Synthesis Constraints
Optimization Methodology
DFT enabled circuit analysis and fault coverage
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