Application of DFT technique

DFT techniques provide controllability and observability. Automatic Test Pattern Generation (ATPG) is used for combinational design and DFT is used for sequential circuits.

Basically two methodologies are followed in the industry.

They are:

1. Scan DFT
2. Built In Self Test (BIST)

Under scan DFT two sub categories are available known as full scan and partial scan. Generally tools support only full scan DFT. Built in DFT compiler of Design Compiler provide multiplexed full scan DFT.

Two ways can be followed while inserting DFT elements to the design. The first one is to compile the design first and then insert scan elements. The second method is to insert scan elements to DFT and then compile.

To check whether design has any DFT rule violations dft_drc command is used. dft_drc check can be enabled by using commands set hdlin_enable_rtldrc_info true and set test_enable_dft_drc true. A test clock for DFT is generated using command create_test_clock clock waveform {25 50}. Period of the test clock is always greater than the original clock period. Total number of scan paths and methodology used are instructed using the command create_test_protocol. Longest chain length in a scan path can also be specified. As per power report, this constraint increases power consumption. insert_scan or insert_dft command converts all Flip Flops to scan registers.

Below is the log data from DFT compiler (in built in Design Compiler). The design synthesized is 3x3 Systolic Array Matrix Multiplier.

Information: Using default scan style 'multiplexed_flip_flop'. (TESTDB-279)
Loading db file '/home/Master_Files/Libraries/gtech.db'
Loading target library 'gtech'
Loading design ...
Starting rtldrc ...
Initializing rtldrc ...
Starting rule checks ...


Information: Scan style is 'multiplexed_flip_flop'. (TEST-1212)

Information: Starting test protocol creation. (TEST-219)
...reading user specified clock signals...
Information: Identified system/test clock port clock (25.0,50.0). (TEST-265)
...reading user specified asynchronous signals...
Loading test protocol
Loading target library 'cb13fs120_tsmc_max'
Loading target library 'cb13io320_tsmc_max'
Warning: IO pad 'pc3d10' is unusable: unknown logic function. (OPT-1022)
Warning: IO pad 'pc3d00' is unusable: unknown logic function. (OPT-1022)
Loading design 'sam3'
Pre-DFT DRC enabled

Information: Starting test design rule checking. (TEST-222)
...basic checks...
...basic sequential cell checks...
...checking for scan equivalents...
...checking vector rules...
...checking pre-dft rules...
-----------------------------------------------------------------
DRC Report
Total violations: 0
-----------------------------------------------------------------
Test Design rule checking did not find violations
-----------------------------------------------------------------
Sequential Cell Report
0 out of 467 sequential cells have violations
-----------------------------------------------------------------
SEQUENTIAL CELLS WITHOUT VIOLATIONS
* 467 cells are valid scan cells

From the above log data it can be observed that there are no DFT violations in the example design considered here. By default, multiplexed flip flop scan technique is used by the tool as seen in the above log data.

Reference

[1] Himanshu Bhatnagar, Advanced ASIC chip Syntheis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[2] Design Compiler® User Guide, Version X-2005.09, September 2005

Related Articles

Synthesis Constraints
Optimization Methodology
DFT enabled circuit analysis and fault coverage