Synthesis Constraints

Let us discuss something about ASIC front end design and its related issues. I would like post some articles related to synthesis constraints, DFT and formal verification. I will consider Synopsys tools to support the discussion.

Three types of constraints can be set for the design in Design Compiler (DC). They are:

1) DRC constraints
2) Optimization constraints
3) Environmental constraints.

DRC constraints exist in library. DRC constraints can’t be relaxed. They can be chosen from library.

DRC constraints are: set_max_fanout, set_max_transition, set_max_capacitance.

If DRC constraints are not specified, then default values from the library are taken.

Three types of optimizations are possible-area, power and timing. We have optimization constraints related to all these.

set_max_area, set_min_area are area constraints.

Only basic level of power optimization is carried out by DC. Its primary target is to meet timing constraints. set_max_leakege and set_max_dynamic are the two power constraints that can be provided to DC.

Both DRC and optimization constraints follow environmental constraints. Setting up of operating conditions and wire load model falls under environmental constraints. The constraints are: set_operating_conditions, set_wire_load_model and set_wire_load_mode. By default enclosed wire load mode is considered by DC.

Synthesis is timing driven process. Several timing constraints are put to synthesis process of SAMM. No timing specifications may be mentioned for a design. Hence to extract the possible value of clock, derive_timing_constraints command is used. This gives a clock period of ‘x’. A nearest clock period less than ‘x’ can be chosen. This value of clock should satisfy slack requirement of DFT enabled circuit also.

Examples of timing constraints are listed bellow:
->set_clock -period 4.75 clock: Clock period constraint set at 4.75 (210 MHz).

->set_clock_uncertainty –setup 0.475 clock: -ve clock skew can lead to setup violations. Possible value of –ve skew is provided to DC so that it can model for that. Generally setup uncertainty is taken as 10% of the clock.

->set_clock_uncertainty –hold 0.27 clock: +ve clock skew can lead to hold violations. Possible value of +ve skew is provided to DC so that it can model for that. Generally hold uncertainty is taken as 5% of the clock.

->set_clock_latency 0.45 clock: This provides possible network latency constraint to DC.

->set_clock_latency –source 0.4 clock: Source latency of 0.45 is selected.

->set_clock_transition 0.04 clock: Clock transition time of 0.04 is modeled.

->set_input_delay 0.40 [all_inputs]: Input delay of 0.4 is set to all inputs.

->remove_input_delay [get_ports clock]: Constraining clock with input delay leads to wrong timing analysis. To exclude clock port from the input delay this command is used.

->set_output_delay 0.40 [all_outputs]: Output delay of 0.4 is provided. If all outputs are registered this delay does not affect the timing analysis.

I/O ports of the design become pads of the IC. Hence tool has to be informed about this so that it analyzes delay, area and power appropriately. This is done using command set_port_is_pad, which sets the I/O ports as pad and insert_pad, which inserts pad.

Reference

[1] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[2] Design Compiler® User Guide, Version X-2005.09, September 2005

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