Introduction to Interconnect Technologies

Interconnects are dominating in deep sub micron level VLSI design due to decreasing wire pitch. Increased complexities of circuits die size are also increasing. Planar 2-D ICs may not fulfill the requirement of heterogeneous integration of different technologies in single IC. As technology nodes advanced below 250nm, interconnect delays started dominating heavily. The introduction of Cu/low-k interconnects provided lesser resistivity and hence reduced delay. But in deep submicron domain (bellow 130 nm) even these interconnects added considerable delay due to increased resistivity owing several material limitations. [1-4]. Interconnected related problems like increased delay and power consumption are tackled by 3-D ICs which shorten the total interconnect length. [1][5].This part of the article series discusses these issues mainly based on reference [1].

Reference

[1] Kaustav Banerjee, Shukri J. Souri, Pawan Kapur, And Krishna C. Saraswat, 3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration, Proceedings Of The IEEE, pp.602-633,Vol. 89, NO. 5, May 2001, 0018–9219/01, 2001, IEEE

[2] Kaustav Banerjee, Shukri J. Souri, Pawan Kapur and Krishna C. Saraswat, 3-D Heterogeneous ICs: A Technology for the Next Decade and Beyond, 5th IEEE Workshop On Signal Propagation On Interconnects, Venice, Italy May, 13-16, 2001
[3] Jason Cong, An Interconnect-Centric Design Flow for Nanometer Technologies, Proceedings of the IEEE, pp.505-528, VOL. 89, No. 4, April 2001, 0018–9219/01,2001 IEEE
[4] Sungjun Im, Navin Srivastava, Kaustav Banerjee, and Kenneth E. Goodson, Thermal Scaling Analysis of Multilevel Cu/Low-k Interconnect Structures in Deep Nanometer Scale Technologies, Proceedings of the 22nd International VLSI Multilevel Interconnect Conference (VMIC), Oct. 3 - 6, Fremont, CA, pp. 525-530, 2005.
[5] Demystifying 3D ICs: The pros and cons of going vertical, http://www.ece.ncsu.edu/muse/papers/dtoc2005.pdf, 9/5/2007

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