The techniques are:
- Contact less interconnect
Each 3-D technology has its own pros and cons. However, all of them provide better handling of interconnect delays in very deep sub micron devices. Comparisons of the method of assembly (die-scale or wafer-scale), maximum number of tiers, vertical interconnects pitch and the amount of routing resources consumed on the chip is shown in Table (1). Figure (1) shows a summary of different 3D interconnect approaches.
Table (1) Comparison of Vertical Interconnect Technologies 
Individual die are stacked and wire-bonded in this technique. Connections between chips are made through the board or chip-carrier and back to other chips in the stack. This approach is limited by the resolution of wire-bonders (35µm and 15µm) and larger number of I/Os in the IC stack limit the wire-bond technique. To protect the pad from tearing off due to mechanical stresses during bond process, all metal layers are required.
In this technology connections are made using solder or gold bumps on the surface of die. Typically the pitch of the bumps is 50-500µm. Epoxy routing tier has micro bump bonded to it and this brings the signals to the edges of the cube, these different tiers are then stacked together. Since assembly related mechanical stresses are less the pads require maximum two layers. Here dies are assembled into a cube. Compared to wire bond technology micro bump technology provide greater vertical interconnect density. Since signals have to be routed to the periphery of the chip no significant reduction of parasitic capacitance can be achieved. Heat generated inside the cube limits the number of tiers that can be stacked. As observed by the authors in  with proper placement of blocks in the 3D architecture, the use of high-power dynamic logic circuits, repeaters, pipelined stages long routing paths could be reduced and this decreases overall power consumption by 15% while simultaneously increasing performance by 15%.
Figure (1) Different 3-D IC technologies 
There are two types of through via interconnect technologies available. They are: through via bulk and through via Silicon on Insulator (SOI). Both methods have the potential to offer the greatest interconnect density with disadvantage of the greatest cost. The first and second wafers are placed face to face and as the tier grows higher layers are placed face to back. Connection is provided by filling tungsten in etched wafers. The next chip sits on the polished surface of the previously etched chip. Power, ground, and I/O connectivity is provided by the top tier. Number of tiers is mainly limited by the heat generated inside the stack. Lesser the tier number higher is the yield. Through via Silicon on Insulator technology has achieved smallest inter tier pitch of the order of 5µm. all layers in the upper tiers and the top layer in the lower tier is consumed in this technology.
Contact less interconnect technology
Contact less or AC-coupled interconnect use capacitive or inductive coupling to communicate between tiers. This method eliminates the signal interconnect connection to the periphery of the IC as well as inter-tier routing. Half capacitors formed by top level of metal are used on capacitive coupling. The distance between the tiers, the rise/fall times of the technology, and the dielectric constant of the gap decide the density of these interconnects. Half capacitors approach requires the tiers to be face-to-face. This limits the number of tiers to two. Power supply between chips is provided by the help of bumps. The distance between two half plates should be small. Either high-k dielectric or trench formation is used to achieve better capacitive coupling. Inductive coupling is more suitable wherein separation of the coupling elements is of the order of lateral dimension of the coupling elements.
 Kaustav Banerjee, Shukri J. Souri, Pawan Kapur, And Krishna C. Saraswat, 3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration, Proceedings Of The IEEE, pp.602-633,Vol. 89, NO. 5, May 2001, 0018–9219/01, 2001, IEEE
 Kaustav Banerjee, Shukri J. Souri, Pawan Kapur and Krishna C. Saraswat, 3-D Heterogeneous ICs: A Technology for the Next Decade and Beyond, 5th IEEE Workshop On Signal Propagation On Interconnects, Venice, Italy May, 13-16, 2001
 Jason Cong, An Interconnect-Centric Design Flow for Nanometer Technologies, Proceedings of the IEEE, pp.505-528, VOL. 89, No. 4, April 2001, 0018–9219/01,2001 IEEE
 Sungjun Im, Navin Srivastava, Kaustav Banerjee, and Kenneth E. Goodson, Thermal Scaling Analysis of Multilevel Cu/Low-k Interconnect Structures in Deep Nanometer Scale Technologies, Proceedings of the 22nd International VLSI Multilevel Interconnect Conference (VMIC), Oct. 3 - 6, Fremont, CA, pp. 525-530, 2005.
 Demystifying 3D ICs: The pros and cons of going vertical, http://www.ece.ncsu.edu/muse/papers/dtoc2005.pdf, 9/5/2007