3-D chip design strategy

It is clear from previous discussions that with the ever increasing chip complexity and functionalities interconnect delay problems are going to be worse in very deep submicron technology. 3-D IC (or interconnect) technologies such as wire-bonding, micro-bumps, through-vias, and contact less interconnect are promising solution for interconnect delay concerns. This technique helps in effective large scale integration of different systems on a single IC.

3-D IC design architecture consists of a number of blocks which are divided from a 2-D chip(s). Different silicon layers are stacked one above the other and different blocks are placed on different layers, known as “tier”. Multiple layer of interconnects can be constructed in each Si tier. These interconnects are linked by vertical interconnects. By routing vertical interconnects appropriately long wire length can be shortened. Multiple active routing layers enhances the options to place the critical path components close to each other thereby decreasing RC delay and significantly improve performance of the design. Global interconnects are made common to all layers. Long wire inter-block communication delay is eliminated by placing these blocks in different layers and connecting them by a vertical interconnect. Thus system design becomes flexible with 3-D IC architecture. Three-dimensional integration can reduce the wiring and hence reduce the capacitance, power dissipation, and chip area and therefore improve overall performance of the chip.

The powerful advantage of 3-D chip design methodology can be exploited to build System on Chips (SoCs). Circuits with different voltage and performance requirements such as digital and analog components in the mixed-signal systems can be placed in different layers as shown in the Figure (1).

Figure (1) Block representation of 3-D IC [5]

Blocks are placed in different layers have lesser electromagnetic interference noise. This can achieve better noise performance of the intended design. High performance SoCs requires synchronous clock distribution. At the topmost layer of the 3-D IC optical interconnects and I/Os can be employed to achieve this.


[1] Kaustav Banerjee, Shukri J. Souri, Pawan Kapur, And Krishna C. Saraswat, 3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration, Proceedings Of The IEEE, pp.602-633,Vol. 89, NO. 5, May 2001, 0018–9219/01, 2001, IEEE

[2] Kaustav Banerjee, Shukri J. Souri, Pawan Kapur and Krishna C. Saraswat, 3-D Heterogeneous ICs: A Technology for the Next Decade and Beyond, 5th IEEE Workshop On Signal Propagation On Interconnects, Venice, Italy May, 13-16, 2001

[3] Jason Cong, An Interconnect-Centric Design Flow for Nanometer Technologies, Proceedings of the IEEE, pp.505-528, VOL. 89, No. 4, April 2001, 0018–9219/01,2001 IEEE

[4] Sungjun Im, Navin Srivastava, Kaustav Banerjee, and Kenneth E. Goodson, Thermal Scaling Analysis of Multilevel Cu/Low-k Interconnect Structures in Deep Nanometer Scale Technologies, Proceedings of the 22nd International VLSI Multilevel Interconnect Conference (VMIC), Oct. 3 - 6, Fremont, CA, pp. 525-530, 2005.

[5] Demystifying 3D ICs: The pros and cons of going vertical, http://www.ece.ncsu.edu/muse/papers/dtoc2005.pdf, 9/5/2007

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