1. Reduction of interconnect delay
It is clear from above discussions that interconnects delay contribute significant portion of the overall path delay. Critical path might have been a result of improper placement of logic cells due to design constraints. Long interconnect delays contribute more towards the timing violations. In such scenarios placing logic blocks in different silicon layers can minimize the interconnect length and hence the critical path delay.
2. Microprocessor Design
Generally in microprocessor designs on-chip cache is physically located on the corner of the die. The logics which access cache memory are distributed apart. Due to this reason, on-chip cache memory is involved in most of the critical paths in microprocessor design. By employing 3-D IC design strategy cache memory and related logical blocks can be placed close one over the other in different tiers. By this arrangement closer proximity of the on-chip cache is assured.
If LxL is the dimension of the processor then the worst case interconnect length in a critical path is 2L. If on-chip cache is placed in second active layer then the worst cases interconnect length is √ (2L). This means reduction of interconnect length by 30%. 3-D IC also improves access time memory in microprocessors.
3. Mixed Signal Integrated Circuits
2-D approach of System on Chip (SoC) integration causes several serious design issues. Switching noise from digital circuit creeps into analog and RF circuits and degrades the fidelity of the analog signals. 3-D IC integration can solve these problems effectively. Analog related all circuits can be realized in separate tier with different technology and can be integrated with digital circuits, which is in a separate layer. Such methodology provides very good noise isolation very much essential for mixed signal circuits.