Advanced Tools in Reconfigurable Computing

HW/SW Co-Design Languages/Tools can be broadly classified into high level languages and extending HDL languages.

High level languages- C-FPGA environment

Direct mapping of C code to configuration level is possible. The software supports emulation and simulation of compiled code for debugging. The software is also capable of handling multiprocessor and multi-FPGA computational definitions. Generally this environment allows explicit data flow control within memory hierarchy. It can produce “Unified Executables” for HW or SW processor execution. The runtime libraries handle required interfacing and management. Some of the important C based mappers used for SoC designs are described below. [5]

• SpecC: This is an extension of ANSI-C. Both behavioral and structural hierarchical embedded systems designs are supported. The language is developed for synthesis and verification in mind. But language is targeted for system-level design language intended for specification and architectural modeling.

• HardwareC: This modified C language uniformly incorporates both functionality and design constraints.

• SystemC from Open SystemC Initiative (OSCI): This C language very much popular in the system level verification industry. It uses C++ class libraries and simulation kernel for creating behavioral and RTL designs. This is Open-source extension of C++ for HW/SW modelling. It includes modules and ports for defining structure, and interfaces and channels. The language supports functional modelling of the design. The language supports hierarchical decomposition of a system into modules. It provides structural connectivity between modules using ports. Events help in scheduling and synchronization of concurrent processes.

• Catapult C from Mentor Graphics: this is an algorithmic synthesis tool for RTL generation. It can generate RTL from pure C++. It does not require any extensions, pragmas, etc. The compiler uses “wrappers” around algorithmic code. This gives capability to manage external I/O interface. Internally it can constrain synthesis to optimize for chosen interface. Architectural constraints and optimization are explicitly mentioned. The tool can generate output RTL netlists in VHDL, Verilog, and SystemC.

• DIME-C from Nallatech: This is a FPGA prototyping tool. The designs are not cycle-accurate. But allows application synthesis for a higher clock speed. The compiler includes IEEE-754 FP cores. It has dedicated integer multipliers. The compiler supports pipeline or parallel optimization. Output produced is synthesizable VHDL and DIMEtalk components.

• Handel C from Celoxica: The tool provides good environment for cycle-accurate application development. All operations occur in one deterministic clock cycle. This feature makes it cycle-accurate. On the flip side of it clock frequency is reduced to slowest operation. Explicitly defined parallelism is achieved in language by the help of pragmas. The compiler can efficiently analyze, optimize, and rewrite code. The output generated from the compiler is VHDL or Verilog, SystemC, or targeted EDIFs.

• Impulse C from Impulse Accelerated Technologies: Sequential applications can be modelled using this language. It can process independent, potentially concurrent, computing blocks. Utilizing Streams-C methodology it can communicate and synchronize processes. It also focuses on compatibility with C development environments. Compilation is carried out by considering each process as separate state machine. Output can be generated in two ways-either generic or FPGA specific VHDL.

• Mitrion C from Mitrion: The language uses concept of “Soft-core” processor. The soft-core processor creates abstraction layer between C code and FPGA. Compilation of C code is achieved by mapping it to a generic “API” of possible functions. Specific application oriented processor is instantiated on FPGA. The soft-core processor supports custom instruction bit-widths, specific cache and buffer sizes. The language can produce outputs as VHDL IP core for the selected target FPGA architectures.

• Napa C from National Semiconductor: This Language/compiler is intended for RISC or FPGA hybrid processors. It capitalize on single-cycle interconnect instead of I/O bus. It uses datapath synthesis technique. From C loops the compiler generates hardware pipelines. The language basically targets National Semiconductor NAPA1000 hybrid processor. It has Fixed-Instruction Processor (FIP) and Adaptive Logic Processor (ALP) which allow programmer to specify whether the section of the code is to be executed in software or hardware. [5]. Outputs generated from the compiler are RTL VHDL, structural VHDL and structural Verilog.

• SA-C from Colorado State University: This is a High-level, expression-oriented, machine-independent, single-assignment language. This is designed to implicitly express data-parallel operations such as image and signal processing. The compiler can perform loop optimizations, structural transforms and execution block placement.

• Streams C from Los Alamos National Laboratory: This is stream-oriented sequential process modelling language. Data elements are moved through discrete functional blocks. The compiler can generate multi-threaded processor executables and multiple FPGA bitstreams. Tha language allows parallel C program translation into a parallel design. Attractive feature of this language is this includes functional-level simulation environment. The compiler produces synthesizable RTL output.

• Java Based Approaches-JHDL: Java HDL language is capable of converting Java into synthesizable HDL code. The JBits Application Programming Interface (API) is implemented in the Java programming language and permits programmatic access to all of the configurable elements in Xilinx Virtex-II FPGAs. JBits 3.0 complements Xilinx's industry leading ISE software tools and enables the design and generation of partial bitstreams for reconfigurable applications.

• UML: Unified Modeling Language: This approach is used for System level modeling. UML is extended so that it can be applied as high level models working with other languages. UML profile for SystemC- this is another extension of the available languages that enables specify, analyze, design, construct, view software and hardware artifacts in a SoC design flow. Extending HDL Languages.

• System Verilog: this language blends both Verilog and C.This language is an extension to IEEE 1364-2001 Verilog. The language supports interfaces that allow module connections at a high level of abstraction.

• SuperLog: This language is Verilog superset that includes constructs from C. Verliog 2001 and SuperLog at two ends of the spectrum. For a very productive design process the language utilizes power of C with the simplicity of Verilog. MATLAB to FPGA Design IP Core Instantiation. Xilinx has DSP system generation tool.

• Khorus: This is a special data flow tool for image processing.

• Ptolomey: This is a graphical entry tool for system level design.

Spectrum of C-based application mappers are shown in Figure (1) and Figure (2).

Figure (1) C-based Application Mappers 1 [2]

Figure (2) C-based Application Mappers 2 [2]

Advantages of C-based application mappers

High level languages are popular for many years are skilled engineers are available in this segment. This enables potential RC users with high-level languages. Due to this required HDL knowledge is significantly reduced or eliminated. Time to preliminary results is much less than manual HDL designs methodology. Software-to-hardware porting is considerably easier due to the portioning of the design. Visualization of C hardware is far easier compared to the HDLs for engineering community. Understanding of any C based mappers is straight forward.

Disadvantages of C-based application mappers

Mapper instructions are several times more powerful than CPU instructions. On the other hand FPGA clocks are many times slower. Due to the hardware nature of mappers they parallelize and pipeline C code, however they generally cannot automatically instantiate multiple functional units. Manual parallelization of existing code using techniques pertinent to algorithm’s structure is necessary to optimize C-mapper code. Performance may degrade at the benefit of reduced development time. Available tools are not capable of automatic translation of codes. Programs still require manual assistance for hardware compilation. Optimized software C is not efficient as optimized Hardware C.

At least two major challenges remain to be addressed. Input/output interfaces become a limiting factor as once a generic I/O wrapper is generated, it should be reusable. True hardware debugging remains a challenge. Since there is no idea internal HDL signals higher level abstraction increases complexity. C and C++ family of languages mainly deal with 32 bit precision which is overhead for most embedded applications. [5]

Advanced Hardwares

There are several hard wares platforms available for reconfigurable computing applications. They provide advanced features which are out performing the standard processors. Some of them are mentioned below.

Xilinx

The Xilinx XC6200 FPGA-based Reconfigurable Co-processor provides open architecture FPGA (XC6200). They provide advanced dynamic reconfiguration capability such as high-speed reconfiguration via parallel CPU interface, full or partial reconfiguration or context switching and unlimited re-programmability.

Figure (3) Xilinx-based application acceleration module [9]

Xilinx Vertex series of processors have 4 Power PC processor embedded within. They support Microblaze soft core processor. Reconfigurable computing has got a major step with the Cray XD1 high-performance computer (see Figure (4) by breaking down performance barriers at substantially lowered cost by using off-the-shelf components from Xilinx to solve difficult computational problems. [9]

Altera

Altera have coprocessor based approach and example FPGAs is ARC-PCI, Compaq Pamette. They have system on chip solutions such as Excalibur device, ARC-PCI. Excalibur device provide embedded processors like ARM, MIPS or NIOS.

Future of Reconfigurable Computing

Several advancements in the field of reconfigurable computing hardware and software are promising greater design flexibility and reduced cost and time to market in embedded system development environments. But the lack of efficient software tools, simpler design methodologies and standards are hindering the complete development of the SoC designs. Engineering community is still not much familiar with the developments of reconfigurable computing domain. High level language based C mappers offer easiness in software development but ignorance of HDL and hardware design methodologies may result in inefficient design which can de motivate the basic power of SoC designs. Advanced FPGAs like Vertex 4 (from Xilinx) and Excalibur (from Altera) are in forefront to provide reconfigurable solutions with third party support.

Related Articles

• Reconfigurable Computing
• Advantages and Disadvantages of Reconfigurable Computing

References

[1] http://www.netrino.com/Articles/RCPrimer/index.php, 10/11/2007

[2] Brian Holland, Mauricio Vacas, Vikas Aggarwal, Ryan DeVille, Ian Troxel, and Alan D. George, Survey of C-based Application Mapping Tools for Reconfigurable Computing, University of Florida, #215 MAPLD 2005

[3] Tirumale K Ramesh, Reconfigurable Computing After a Decade: A New Perspective and Challenges for Hardware-Software Co-Design and Development, Northern Virginia Chapter IEEE Computer Society Meeting, April 14, 2005

[4] T.J. Todman, G.A. Constantinides, S.J.E. Wilton, O. Mencer, W. Luk and P.Y.K. Cheung, Reconfigurable computing: architectures and design Methods, IEE Proc.-Comput. Digit. Tech., Vol. 152, No. 2, pp.193-207, March 2005

[5] Katherine Compton, Scott Hauck, Reconfigurable Computing: A Survey of Systems and Software, ACM Computing Surveys, Vol. 34, No. 2, June 2002, pp. 171–210.

[6] Dr. Steve A. Guccione, Reconfigurable Computing at Xilinx, Proceedings of the Euromicro Symposium on Digital Systems Design (DSD’01), IEEE, 0-7695-1239-9/01,2001

[7] Steven A. Guccione, Delon Levi and Prasanna Sundararajan. JBits: A Java-based Interface for Reconfigurable Computing, 2nd Annual Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD), 1999. http://www.io.com/~guccione/Papers/MAPPLD/JBitsMAPPLD.pdf , 10/11/2007

[8] Joao M. P. Cardoso and Mario P. Vestias, Architectures and Compilers to Support Reconfigurable Computing, www.acm.org/crossroads/xrds5-3/rcconcept.html, 10/11/2007

[9] Geert C, Wenes Steve Margerm, Sriram R. Chelluri, Designing Reconfigurable Computing Solutions, Xcell Journal, First Quarter 2006.

Advantages and Disadvantages of Reconfigurable Computing

Reconfigurable computing has several advantages and drawbacks. They are listed below.

Advantages

• Greater Functionality

It is possible to achieve greater functionality with a simpler hardware design. The required logic can be stored in memory and hence the cost of supporting additional features is reduced to the cost of the memory required to store the logic design. This is very much useful in mobile communication domain where protocol can be easily modified to newer protocol and stored in memory and then hardware can be reconfigured to achieve the required functionality. Compelling advantage includes increased speed, reduced energy and power consumption. A study reports that depending on the particular device used moving critical software loops to reconfigurable hardware results in average energy savings of 35% to 70% with an average speedup of 3 to 7 times. [4]

• Embedded Characteristics

In general-purpose computing processors common piece of silicon could be configured, after fabrication, to solve any computing task. This meant many applications could share commodity economics for the production of a single IC and the same IC could be used to solve different problems at different points in time. General-purpose computing meant engineers could program the component to do things which the original IC manufacturers never conceived. Embedded systems developers are much benefited from reconfigurable computing systems, especially with the introduction of soft cores which can contain one or more instruction processors. [4]

All of these "general-purpose" characteristics are shared by reconfigurable computing. Instead of computing a function by sequencing through a set of operations in time (like a processor), reconfigurable computers compute a function by configuring functional units and wiring them up in space. This allows parallel computation of specific, configured operations, like a custom ASIC. Also it can also be reconfigured. The reconfigurable hardware fabric can be easily and quickly modified from a remote location to upgrade its performance. It can be modified to perform a completely different function. Hence, non-recurring engineering (NRE) costs of reconfigurable computing are lower than that of a custom ASIC.

• Lower System Cost

By eliminating the ASIC design lower system cost on a low-volume product is achieved. For higher-volume products, the production cost of fixed hardware is actually very much lower. In the case of ASIC and general purpose hardware designs technical obsolescence drives up the cost of systems. Reconfigurable computing systems are upgradeable and extend the useful life of the system. This reduces lifetime costs.

• Reduced Time to Market

Reduced time-to-market is the final advantage of reconfigurable computing. Since ASIC is no longer used in reconfigurable computing large amount of development effort is reduced. The logic design remains flexible even after the product is shipped. Design can be sent to market with minimum requirements and later additional features can be added without any change in physical device (or system). Thus reconfigurable computing allows incremental design flow.

These advantages lead reconfigurable computers to serve as powerful tools for many applications. The applications include research and development tools for sophisticated electronic systems such as ASICs and printed circuit boards (PCBs). Simulation tools for these systems do not exist. Also prototype fabrication is expensive and time consuming. A reconfigurable computer can serve as an affordable, fast, and accurate tool for verifying electronic designs

Disadvantages

Two severe disadvantages of reconfigurable computing can be observed. They are the time that the chip takes to reconfigure itself to a given task, and the difficulty in programming such chips. Dynamic reconfigurable computing has several different complex issues. They are design space, placement, routing, timing, consistency and development tools. Each of these is discussed below.

• Placement Issues

In order to reconfigure a new hardware, it requires having ample space to place the new hardware. The component placement issue becomes complex if the component needs to be placed near special resources like built- in memory, I/O pins or DLLs on the FPGA.

• Routing Issues

Existing components has to be connected to the components newly reconfigured. The ports must be available to interface new components. The same ports must have also been used under the old configuration. To accomplish this orientation of the components should be in a workable fashion.

• Timing Issues

Newly configured hardware must meet the timing requirement for the efficient operation of the circuit. Longer wires between components may affect the timing. Optimal speed should be attainable after dynamically reconfiguring the device. Over timing or under timing the new added design may yield erroneous result.

• Consistency Issues

Static or dynamic reconfiguration of the device should not degrade computational consistency of the design. This issue becomes critical when the FPGA is partially reconfigured and interfaced with existing design. Adding new components to the device by reconfigurable fabric should not erase or alter the existing design in the device. (Or memory). There should be some safe methods to store the bit stream to the memory.

• Development Tools

Commercial development tools for dynamic reconfigurable computing are still under development stage. The lack of commercially available tools for the specification to implementation stages of the digital design is still a bottleneck. The available tools require enormous human intervention to implement the complete system.

Related Articles

• Reconfigurable Computing
• Advanced Tools in Reconfigurable Computing

References

[1] http://www.netrino.com/Articles/RCPrimer/index.php, 10/11/2007

[2] Brian Holland, Mauricio Vacas, Vikas Aggarwal, Ryan DeVille, Ian Troxel, and Alan D. George, Survey of C-based Application Mapping Tools for Reconfigurable Computing, University of Florida, #215 MAPLD 2005

[3] Tirumale K Ramesh, Reconfigurable Computing After a Decade: A New Perspective and Challenges for Hardware-Software Co-Design and Development, Northern Virginia Chapter IEEE Computer Society Meeting, April 14, 2005

[4] T.J. Todman, G.A. Constantinides, S.J.E. Wilton, O. Mencer, W. Luk and P.Y.K. Cheung, Reconfigurable computing: architectures and design Methods, IEE Proc.-Comput. Digit. Tech., Vol. 152, No. 2, pp.193-207, March 2005

[5] Katherine Compton, Scott Hauck, Reconfigurable Computing: A Survey of Systems and Software, ACM Computing Surveys, Vol. 34, No. 2, June 2002, pp. 171–210.

[6] Dr. Steve A. Guccione, Reconfigurable Computing at Xilinx, Proceedings of the Euromicro Symposium on Digital Systems Design (DSD’01), IEEE, 0-7695-1239-9/01, 2001

[7] Steven A. Guccione, Delon Levi and Prasanna Sundararajan. JBits: A Java-based Interface for Reconfigurable Computing, 2nd Annual Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD), 1999. http://www.io.com/~guccione/Papers/MAPPLD/JBitsMAPPLD.pdf , 10/11/2007

[8] Joao M. P. Cardoso and Mario P. Vestias, Architectures and Compilers to Support Reconfigurable Computing, www.acm.org/crossroads/xrds5-3/rcconcept.html, 10/11/2007

[9] Geert C, Wenes Steve Margerm, Sriram R. Chelluri, Designing Reconfigurable Computing Solutions, Xcell Journal, First Quarter 2006.

Reconfigurable Computing

Processing power is the main concern of today’s computationally intensive applications such as streaming video, image recognition and processing. In the embedded market power consumption target, packaging and manufacturing cost, time to market requirements are decreasing rapidly. Meeting these constraints are more challenging than ever before.

Such processing requirements can be fulfilled by 3 ways [3] [5]:

• High-performance microprocessors
• Application-specific integrated circuits (ASIC)
• Reconfigurable computing (RC) systems

• High-performance microprocessors

High-performance microprocessors provide an off the-shelf means of addressing processing requirements. Unfortunately for many applications, a single processor is not fast enough. In addition, the power consumption (of the order of 100W or more) and cost (thousands of dollars) of these processors limit their applications in embedded field.

• Application-specific integrated circuits (ASIC)

An ASIC implementation provides means of implementing the design in large amount of parallelism. This custom hardware is faster and more compact than general-purpose hardware. ASIC avoids instruction fetch, decode and execution by large amount. ASICs consume less power than reconfigurable devices. An ASIC can contain just the right mix of functional units for a particular application. But ASICs, they are uneconomical for many embedded systems due to the production (mask and device) cost and the time to market (can be 6 months).Only the very highest-volume applications and lower per-unit price warrant the high nonrecurring engineering (NRE) cost of designing an ASIC.

• Reconfigurable computing (RC) systems

A reconfigurable computing system typically contains one or more processors and a reconfigurable fabric upon which custom functional units can be built.

Organization of RC systems with respect to the coupling of the RPU to the host computer is shown in Figure (1). The processor(s) executes sequential and non-critical code, HDL is mapped to reconfigurable fabric. Reconfigurable logic provides advantage of the parallelism. RCs based on Field Programmable Gate Arrays (FPGAs) are an attractive alternative. The resulting FPGA combines the best of both general purpose and custom IC. It is faster and smaller than general-purpose hardware, yet compared to an IC, it has smaller NRE costs and transition costs. FPGAs can be easily re-customized without modifying the hardware by designing and loading a different configuration. A reconfigurable computer could be upgraded, or even reconfigured for a completely different function, from a remote location.

Figure (1) Organization of RC systems with respect to the coupling of the RPU to the host computer [8]

Related Articles

• Advantages and Disadvantages of Reconfigurable Computing
• Advanced Tools in Reconfigurable Computing

References

[1] http://www.netrino.com/Articles/RCPrimer/index.php, 10/11/2007

[2] Brian Holland, Mauricio Vacas, Vikas Aggarwal, Ryan DeVille, Ian Troxel, and Alan D. George, Survey of C-based Application Mapping Tools for Reconfigurable Computing, University of Florida, #215 MAPLD 2005

[3] Tirumale K Ramesh, Reconfigurable Computing After a Decade: A New Perspective and Challenges for Hardware-Software Co-Design and Development, Northern Virginia Chapter IEEE Computer Society Meeting, April 14, 2005

[4] T.J. Todman, G.A. Constantinides, S.J.E. Wilton, O. Mencer, W. Luk and P.Y.K. Cheung, Reconfigurable computing: architectures and design Methods, IEE Proc.-Comput. Digit. Tech., Vol. 152, No. 2, pp.193-207, March 2005

[5] Katherine Compton, Scott Hauck, Reconfigurable Computing: A Survey of Systems and Software, ACM Computing Surveys, Vol. 34, No. 2, June 2002, pp. 171–210.

[6] Dr. Steve A. Guccione, Reconfigurable Computing at Xilinx, Proceedings of the Euromicro Symposium on Digital Systems Design (DSD’01), IEEE, 0-7695-1239-9/01, 2001

[7] Steven A. Guccione, Delon Levi and Prasanna Sundararajan, JBits: A Java-based Interface for Reconfigurable Computing, 2nd Annual Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD), 1999. http://www.io.com/~guccione/Papers/MAPPLD/JBitsMAPPLD.pdf , 10/11/2007

[8] Joao M. P. Cardoso and Mario P. Vestias, Architectures and Compilers to Support Reconfigurable Computing, www.acm.org/crossroads/xrds5-3/rcconcept.html, 10/11/2007

[9] Geert C, Wenes Steve Margerm, Sriram R. Chelluri, Designing Reconfigurable Computing Solutions, Xcell Journal, First Quarter 2006.