10 November 2007

Reconfigurable Computing

Processing power is the main concern of today’s computationally intensive applications such as streaming video, image recognition and processing. In the embedded market power consumption target, packaging and manufacturing cost, time to market requirements are decreasing rapidly. Meeting these constraints are more challenging than ever before.


Such processing requirements can be fulfilled by 3 ways [3] [5]:

  • High-performance microprocessors
  • Application-specific integrated circuits (ASIC)
  • Reconfigurable computing (RC) systems


  • High-performance microprocessors

High-performance microprocessors provide an off the-shelf means of addressing processing requirements. Unfortunately for many applications, a single processor is not fast enough. In addition, the power consumption (of the order of 100W or more) and cost (thousands of dollars) of these processors limit their applications in embedded field.

  • Application-specific integrated circuits (ASIC)

An ASIC implementation provides means of implementing the design in large amount of parallelism. This custom hardware is faster and more compact than general-purpose hardware. ASIC avoids instruction fetch, decode and execution by large amount. ASICs consume less power than reconfigurable devices. An ASIC can contain just the right mix of functional units for a particular application. But ASICs, they are uneconomical for many embedded systems due to the production (mask and device) cost and the time to market (can be 6 months).Only the very highest-volume applications and lower per-unit price warrant the high nonrecurring engineering (NRE) cost of designing an ASIC.

  • Reconfigurable computing (RC) systems

A reconfigurable computing system typically contains one or more processors and a reconfigurable fabric upon which custom functional units can be built.

Organization of RC systems with respect to the coupling of the RPU to the host computer is shown in Figure (1). The processor(s) executes sequential and non-critical code, HDL is mapped to reconfigurable fabric. Reconfigurable logic provides advantage of the parallelism. RCs based on Field Programmable Gate Arrays (FPGAs) are an attractive alternative. The resulting FPGA combines the best of both general purpose and custom IC. It is faster and smaller than general-purpose hardware, yet compared to an IC, it has smaller NRE costs and transition costs. FPGAs can be easily re-customized without modifying the hardware by designing and loading a different configuration. A reconfigurable computer could be upgraded, or even reconfigured for a completely different function, from a remote location.




Figure (1) Organization of RC systems with respect to the coupling of the RPU to the host computer [8]


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References

[1] http://www.netrino.com/Articles/RCPrimer/index.php, 10/11/2007

[2] Brian Holland, Mauricio Vacas, Vikas Aggarwal, Ryan DeVille, Ian Troxel, and Alan D. George, Survey of C-based Application Mapping Tools for Reconfigurable Computing, University of Florida, #215 MAPLD 2005

[3] Tirumale K Ramesh, Reconfigurable Computing After a Decade: A New Perspective and Challenges for Hardware-Software Co-Design and Development, Northern Virginia Chapter IEEE Computer Society Meeting, April 14, 2005

[4] T.J. Todman, G.A. Constantinides, S.J.E. Wilton, O. Mencer, W. Luk and P.Y.K. Cheung, Reconfigurable computing: architectures and design Methods, IEE Proc.-Comput. Digit. Tech., Vol. 152, No. 2, pp.193-207, March 2005

[5] Katherine Compton, Scott Hauck, Reconfigurable Computing: A Survey of Systems and Software, ACM Computing Surveys, Vol. 34, No. 2, June 2002, pp. 171–210.

[6] Dr. Steve A. Guccione, Reconfigurable Computing at Xilinx, Proceedings of the Euromicro Symposium on Digital Systems Design (DSD’01), IEEE, 0-7695-1239-9/01, 2001

[7] Steven A. Guccione, Delon Levi and Prasanna Sundararajan, JBits: A Java-based Interface for Reconfigurable Computing, 2nd Annual Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD), 1999. http://www.io.com/~guccione/Papers/MAPPLD/JBitsMAPPLD.pdf , 10/11/2007

[8] Joao M. P. Cardoso and Mario P. Vestias, Architectures and Compilers to Support Reconfigurable Computing, www.acm.org/crossroads/xrds5-3/rcconcept.html, 10/11/2007

[9] Geert C, Wenes Steve Margerm, Sriram R. Chelluri, Designing Reconfigurable Computing Solutions, Xcell Journal, First Quarter 2006.

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