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Advantages and Disadvantages of Reconfigurable Computing

Reconfigurable computing has several advantages and drawbacks. They are listed below.


  • Greater Functionality

It is possible to achieve greater functionality with a simpler hardware design. The required logic can be stored in memory and hence the cost of supporting additional features is reduced to the cost of the memory required to store the logic design. This is very much useful in mobile communication domain where protocol can be easily modified to newer protocol and stored in memory and then hardware can be reconfigured to achieve the required functionality. Compelling advantage includes increased speed, reduced energy and power consumption. A study reports that depending on the particular device used moving critical software loops to reconfigurable hardware results in average energy savings of 35% to 70% with an average speedup of 3 to 7 times. [4]

  • Embedded Characteristics

In general-purpose computing processors common piece of silicon could be configured, after fabrication, to solve any computing task. This meant many applications could share commodity economics for the production of a single IC and the same IC could be used to solve different problems at different points in time. General-purpose computing meant engineers could program the component to do things which the original IC manufacturers never conceived. Embedded systems developers are much benefited from reconfigurable computing systems, especially with the introduction of soft cores which can contain one or more instruction processors. [4]

All of these "general-purpose" characteristics are shared by reconfigurable computing. Instead of computing a function by sequencing through a set of operations in time (like a processor), reconfigurable computers compute a function by configuring functional units and wiring them up in space. This allows parallel computation of specific, configured operations, like a custom ASIC. Also it can also be reconfigured. The reconfigurable hardware fabric can be easily and quickly modified from a remote location to upgrade its performance. It can be modified to perform a completely different function. Hence, non-recurring engineering (NRE) costs of reconfigurable computing are lower than that of a custom ASIC.

  • Lower System Cost

By eliminating the ASIC design lower system cost on a low-volume product is achieved. For higher-volume products, the production cost of fixed hardware is actually very much lower. In the case of ASIC and general purpose hardware designs technical obsolescence drives up the cost of systems. Reconfigurable computing systems are upgradeable and extend the useful life of the system. This reduces lifetime costs.

  • Reduced Time to Market

Reduced time-to-market is the final advantage of reconfigurable computing. Since ASIC is no longer used in reconfigurable computing large amount of development effort is reduced. The logic design remains flexible even after the product is shipped. Design can be sent to market with minimum requirements and later additional features can be added without any change in physical device (or system). Thus reconfigurable computing allows incremental design flow.

These advantages lead reconfigurable computers to serve as powerful tools for many applications. The applications include research and development tools for sophisticated electronic systems such as ASICs and printed circuit boards (PCBs). Simulation tools for these systems do not exist. Also prototype fabrication is expensive and time consuming. A reconfigurable computer can serve as an affordable, fast, and accurate tool for verifying electronic designs


Two severe disadvantages of reconfigurable computing can be observed. They are the time that the chip takes to reconfigure itself to a given task, and the difficulty in programming such chips. Dynamic reconfigurable computing has several different complex issues. They are design space, placement, routing, timing, consistency and development tools. Each of these is discussed below.

  • Placement Issues

In order to reconfigure a new hardware, it requires having ample space to place the new hardware. The component placement issue becomes complex if the component needs to be placed near special resources like built- in memory, I/O pins or DLLs on the FPGA.

  • Routing Issues

Existing components has to be connected to the components newly reconfigured. The ports must be available to interface new components. The same ports must have also been used under the old configuration. To accomplish this orientation of the components should be in a workable fashion.

  • Timing Issues

Newly configured hardware must meet the timing requirement for the efficient operation of the circuit. Longer wires between components may affect the timing. Optimal speed should be attainable after dynamically reconfiguring the device. Over timing or under timing the new added design may yield erroneous result.

  • Consistency Issues

Static or dynamic reconfiguration of the device should not degrade computational consistency of the design. This issue becomes critical when the FPGA is partially reconfigured and interfaced with existing design. Adding new components to the device by reconfigurable fabric should not erase or alter the existing design in the device. (Or memory). There should be some safe methods to store the bit stream to the memory.

  • Development Tools

Commercial development tools for dynamic reconfigurable computing are still under development stage. The lack of commercially available tools for the specification to implementation stages of the digital design is still a bottleneck. The available tools require enormous human intervention to implement the complete system.

Related Articles


[1], 10/11/2007

[2] Brian Holland, Mauricio Vacas, Vikas Aggarwal, Ryan DeVille, Ian Troxel, and Alan D. George, Survey of C-based Application Mapping Tools for Reconfigurable Computing, University of Florida, #215 MAPLD 2005

[3] Tirumale K Ramesh, Reconfigurable Computing After a Decade: A New Perspective and Challenges for Hardware-Software Co-Design and Development, Northern Virginia Chapter IEEE Computer Society Meeting, April 14, 2005

[4] T.J. Todman, G.A. Constantinides, S.J.E. Wilton, O. Mencer, W. Luk and P.Y.K. Cheung, Reconfigurable computing: architectures and design Methods, IEE Proc.-Comput. Digit. Tech., Vol. 152, No. 2, pp.193-207, March 2005

[5] Katherine Compton, Scott Hauck, Reconfigurable Computing: A Survey of Systems and Software, ACM Computing Surveys, Vol. 34, No. 2, June 2002, pp. 171–210.

[6] Dr. Steve A. Guccione, Reconfigurable Computing at Xilinx, Proceedings of the Euromicro Symposium on Digital Systems Design (DSD’01), IEEE, 0-7695-1239-9/01, 2001

[7] Steven A. Guccione, Delon Levi and Prasanna Sundararajan. JBits: A Java-based Interface for Reconfigurable Computing, 2nd Annual Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD), 1999. , 10/11/2007

[8] Joao M. P. Cardoso and Mario P. Vestias, Architectures and Compilers to Support Reconfigurable Computing,, 10/11/2007

[9] Geert C, Wenes Steve Margerm, Sriram R. Chelluri, Designing Reconfigurable Computing Solutions, Xcell Journal, First Quarter 2006.

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